The major aim of CMP is not the removal of excess material but the planarization of the surface. Therefore the determination of the planarization length appears to be more important than the removal rate itself. It has been shown, that the planarization length is not a constant process parameter, but is related to the removal respectively to the polish time in a square root behaviour. Founded on models proposed by Boning, Ouma, et. al. we applied a sequential polish on a single quasi infinite step. The resulting profile could be simulated by a sequential convolution of the surface contour with a Gaussian transfer function.

To come closer to the situation on a chip pattern we investigated the planarization behaviour on a specific pattern of the MIT854AZ copper CMP test chip, where a large area of unpatterned surface touches a pattern with a specific constant density.

The 200 mm wafer samples consisted of RIE structured oxide films covered with 850 nm ECD copper. The polish was performed on a standard semiconductor manufacturing tool, using a commercial consumables set. The surface profiles were determined by a high resolution profiler within the polishing sequence. The densely patterned areas are removed within a certain polishing time while the transition point between the unpatterned and patterned area appears as a global step. The deposited copper thickness is sufficient to study the contour evolution in both phases, before and after removal of the dense pattern. The paper presents the experimental results on the contour evolution for the patterned fields as well as the global step.