Our experimental studies confirm that changes in a-Si Thin Film Transistors (TFTs) under voltage stress occur in the device channel and not in the contacts. We demonstrate that stressing an a-Si TFT not only shifts the device threshold voltage but can also changes the slope of the semilog subthreshold current dependence on the gate voltage. In addition, stressing can decrease the minimum leakage current. The creation of new localized states in the amorphous silicon under voltage stress qualitatively explains all these effects, while carrier tunneling and trapping in the gate insulator layer cannot by itself explain our data. At large negative gate voltages, the leakage current increases due to the holes injected into the channel. This hole current is also affected by voltage stress as can be predicted by the state creation mechanism.