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Stress and Defect Generation in Si Epitaxy
Published online by Cambridge University Press: 01 February 2011
Abstract
A quasi-static model is proposed to describe wafer deformation due to stress build up in the Si epitaxy process. The analysis takes into account temporal stress variations as the wafer sags into the dish-shaped pocket of the susceptor at a deposition temperature above 1100 °C. It is shown that the magnitude of the negative bending moment at the wafer supporting edge decreases over time. As a result, the maximum deflection at the wafer center and the tensile stress at the wafer supporting edge also decrease over time. The generation of slip defects near the wafer edge as the wafer responds the thermal, gravitational and contact stress is explored. A new test methodology is developed to track the time-varying wafer deflection. It allows for the measurement of quality of the susceptor and its fitness for use in the reactor system.
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- Copyright © Materials Research Society 2004
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