Utilization of radiation damage by means of ion implantation to reduce parasitic capacitances in GaAs integrated circuits has become a well-established technique in the last years. Similar to GaAs, novel high-speed silicon-based devices, e.g. the Si/SiGe heterojunction bipolar transistor, are generally marked by additional short time annealing related to doping activation and a metallization annealing step in the range of 400 °C .

For reproducing the external base region of such devices, Si-p+nn+ diodes were realized and investigated using I-V and C-V measurements. Slight radiation damage was achieved by Ne-implantation. Apart from enhanced leakage currents due to space charge recombination, capacitance reduction for frequencies above 50 kHz was observed even for a n-layer doping concentration as high as 1 to 2x1017 cm-3 including a 12 min 400 °C annealing step. Preliminary tests with 250 keV-Ne-ions within a dose range between 1013 and 1014 cm-2 were carried out with Schottky diodes on moderately doped n-type Si-substrate (0.3 Ωcm). For a high temperature furnace anneal at 900 °C (2 min), no capacitance reduction could be observed.

Compared to previous results with Ar-implantation to obtain amorphized silicon layers, this technique allows a more easy technological handling concerning the metallization and the use of a simple photoresist pattern.