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Simulations of Buffer Layers in a-Si:H Thin Film Solar Cells Deposited with an Expanding Thermal Plasma

Published online by Cambridge University Press:  01 February 2011

A.M.H.N. Petit
Affiliation:
Delft University of Technology, DIMES-ECTM, P.O. Box 5053, 2600 GB Delft, The Netherlands. Eindhoven University of Technology, Department of Applied Physics, P.O. Box 513, 5600 MB Eindhoven, The Netherlands.
M. Zeman
Affiliation:
Delft University of Technology, DIMES-ECTM, P.O. Box 5053, 2600 GB Delft, The Netherlands.
R.A.C.M.M. van Swaaij
Affiliation:
Delft University of Technology, DIMES-ECTM, P.O. Box 5053, 2600 GB Delft, The Netherlands.
M.C.M. van de Sanden
Affiliation:
Eindhoven University of Technology, Department of Applied Physics, P.O. Box 513, 5600 MB Eindhoven, The Netherlands.
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Abstract

With an Expanding Thermal Plasma Chemical Vapor Deposition system (ETP-CVD), solar grade amorphous silicon (a-Si:H) can be deposited at high deposition rate (> 2 nm/s). We think that during the first stage of deposition, a material is grown with a higher defect density than the rest of the bulk creating a defect-rich layer (DRL). Therefore we analyzed, by the means of simulations, the influence of the position of the DRL on the performance of a p-i-n a-Si:H solar cell when moved from the p-i towards the i-n interface and as a function of its thickness. We investigate the effect of a buffer layer in between the p- and the i-layer on the external parameters of the solar cell. The presence of a buffer layer increases the electric field near the p-i interface, which leads to a higher collection of free charge carriers at the interface, although the electric field is then diminished deeper in the bulk. It appears that 10 nm thick buffer layer is sufficient to improve the performance. In case no buffer layer is applied, recombination losses at the p-i interface diminish the performance of the solar cell. We also observe that an increase of the DRL thickness results in a reduction of the solar-cell performance, which is more pronounced when the DRL is located in the region close to the p-i interface rather than close to the i-n interface.

Type
Research Article
Copyright
Copyright © Materials Research Society 2003

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References

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