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A Simple Technique for Sub-10 nm Planar Nanofluidic Channel Fabrication

Published online by Cambridge University Press:  31 January 2011

Chunrong Song  and
Pingshan Wang
Chunrong Song
Affiliation:
[email protected], Clemson University, ECE, Clemson, South Carolina, United States
Pingshan Wang
Affiliation:
[email protected], Clemson University, ECE, Clemson, South Carolina, United States
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Abstract

A simple and low-cost technique is demonstrated to fabricate sub-10 nm planar nanofluidic channels. Native oxide on silicon surface is etched with a multiple hydrofluoric (HF)-etch / SiO2-regrowth process. Shallow Si trenches with 3 nm to 24 nm depths are obtained at an etch rate of 1 nm per HF dip. The trenches are uniform with a surface r.m.s. roughness of 0.4 - 0.6 nm. A low-temperature and low-voltage anodic wafer bonding process is then used to form planar nanofluidic channels. Minimum aspect ratio (depth/width) of the fabricated sub-10 nm nanochannels is around 0.001-0.002.

Keywords

nanoscalenanostructurefluidics
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1222: Symposium DD – Microelectromechanical Systems — Materials and Devices III , 2009 , 1222-DD05-08
Copyright
Copyright © Materials Research Society 2010

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