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SiGe Heteroepitaxy for High Frequency Circuits

Published online by Cambridge University Press:  10 February 2011

B. Tillack ,
D. Bolze ,
G. Fischer ,
G. Kissinger ,
D. Knoll ,
G. Ritter ,
P. Schley  and
D. Wolansky
B. Tillack
Affiliation:
Institute for Semiconductor Physics, Walter-Korsing-Straße 2, 15230 Frankfurt (Oder), Germany, [email protected]
D. Bolze
Affiliation:
Institute for Semiconductor Physics, Walter-Korsing-Straße 2, 15230 Frankfurt (Oder), Germany, [email protected]
G. Fischer
Affiliation:
Institute for Semiconductor Physics, Walter-Korsing-Straße 2, 15230 Frankfurt (Oder), Germany, [email protected]
G. Kissinger
Affiliation:
Institute for Semiconductor Physics, Walter-Korsing-Straße 2, 15230 Frankfurt (Oder), Germany, [email protected]
D. Knoll
Affiliation:
Institute for Semiconductor Physics, Walter-Korsing-Straße 2, 15230 Frankfurt (Oder), Germany, [email protected]
G. Ritter
Affiliation:
Institute for Semiconductor Physics, Walter-Korsing-Straße 2, 15230 Frankfurt (Oder), Germany, [email protected]
P. Schley
Affiliation:
Institute for Semiconductor Physics, Walter-Korsing-Straße 2, 15230 Frankfurt (Oder), Germany, [email protected]
D. Wolansky
Affiliation:
Institute for Semiconductor Physics, Walter-Korsing-Straße 2, 15230 Frankfurt (Oder), Germany, [email protected]
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Abstract

We have determined the process capability of Low Pressure (Rapid Thermal) Chemical Vapor Deposition (LP(RT)CVD) of epitaxial Si/SiGe/Si stacks for heterojunction bipolar transistors (HIBTs). The transistor parameters primarily influenced by the epitaxial characteristics were measured for 600 identically processed 4” wafers. The results demonstrate that it is possible to control accurately the epitaxial process for a 25 nm thick graded SiGe base profile with 20 % Ge and very narrow B doping (5 nm). The pipe limited device yield of about 90 % for an emitter area of 104 μm2 indicates a very low defect density in the epitaxial layer stack. The process capability indices determined from about 40,000 data points demonstrate the stability and capability of the LP(RT)CVD epitaxy with regard to manufacturing requirements.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 525: Symposium W – Rapid Thermal & Integrated Processing VII , 1998 , 379
Copyright
Copyright © Materials Research Society 1998

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References

REFERENCES

1. Harame, D. L. et al., IEDM Tech. Dig., pp. 19–22, (1992).Google Scholar
2. Ahlgren, D. C. et al., IEDM Tech. Dig., pp. 859–862, (1996).Google Scholar
3. Temmler, D. et al., in 1997 Conference on Silicon Heterostructures: From Physics to Devices Tech. Dig., (Eng.Found.1997)Google Scholar
4. Ritter, G., Tillack, B. and Knoll, D., in Thermal and Integrated Processing IV, edited by Brueck, S. R. J., Gelpey, J. C., Kermani, A., Regolini, J. L., Sturm, J. C. (Mater. Res. Soc. Proc. 387, Pittsburgh, RA, 1995) pp. 341–346.Google Scholar
5. Ritter, G. et al. in ESSDERC'97 Tech.Dig., edited by H., Grtinbacher (Editions Frontieres 1997) pp. 424–427.Google Scholar
6. Zaumseil, P., Cryst. Res. Technol. 31, 529 (1996).Google Scholar
7. Taijing, L., Toyoda, K., Nango, N. and Ogawa, T., J. Cryst. Growth, 114, 64 (1991).Google Scholar
8. Kissinger, G. et al., Electrochem. Soc. Proc. Vol. 95–30, 157 (1995)Google Scholar
9. Bowman, R. et al., in Advanced VLSI Fabrication (ICE, 1995), pp. 1017–1022.Google Scholar