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Self-aligned Amorphous Silicon Thin Film Transistors with Mobility above 1 cm2V−1s−1 fabricated at 300°C on Clear Plastic Substrates

Published online by Cambridge University Press:  01 February 2011

Kunigunde H Cherenack ,
Alex Z Kattamis ,
Bahman Hekmatshoar ,
James C Sturm  and
Sigurd Wagner
Kunigunde H Cherenack
Affiliation:
[email protected], Princeton University, Electrical Engineering, B405 E-Quad, Princeton University, Olden Street, Princeton, NJ, 08540, United States
Alex Z Kattamis
Affiliation:
[email protected], Princeton University, Princeton, NJ, 08540, United States
Bahman Hekmatshoar
Affiliation:
[email protected], Princeton University, Princeton, NJ, 08540, United States
James C Sturm
Affiliation:
[email protected], Princeton University, Princeton, NJ, 08540, United States
Sigurd Wagner
Affiliation:
[email protected], Princeton University, Princeton, NJ, 08540, United States
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Abstract

We have developed a fabrication process for amorphous-silicon thin-film transistors (a-Si:H TFTs) on free-standing clear plastic substrates at temperatures up to 300°C. The 300°C fabrication process is made possible by using a unique clear plastic substrate that has a very low coefficient of thermal expansion (CTE < 10ppm/°C) and a glass transition temperature higher than 300°C. Our TFTs have a conventional inverted-staggered gate back-channel passivated geometry, which we designed to achieve two goals: accurate overlay alignment and a high effective mobility. A requirement that becomes particularly difficult to meet in the making of TFT backplanes on plastic foil at 300°C is minimizing overlay misalignment. Even though we use a substrate that has a relatively low CTE, accurately aligning the TFTs on the free-standing, 70-micrometer thick substrate is challenging. To deal with this immediate challenge, and to continue developing processes for free-standing web substrates, we are introducing techniques for self-alignment to our TFT fabrication process. We have self-aligned the channel to the gate by exposing through the clear plastic substrate. To raise the effective mobility of our TFTs we reduced the series resistance by decreasing the thickness of the amorphous silicon layer between the source-drain contacts and the accumulation layer in the channel. The back-channel passivated structure allows us to decrease the thickness of the a-Si:H active layer down to around 20nm. These changes have enabled us to raise the effective field effect mobility on clear plastic to values above 1 cm2V−1s−1

Keywords

thin filmplasma-enhanced CVD (PECVD) (deposition)lithography (removal)
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1066: Symposium A – Amorphous and Polycrystalline Thin-Film Silicon Science and Technology—2008 , 2008 , 1066-A20-03
Copyright
Copyright © Materials Research Society 2008

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