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Schottky Source/Drain Transistor on Thin SiGe on Insulator Integrated with HfO2/TaN Gate Stack

Published online by Cambridge University Press:  01 February 2011

Fei Gao ,
S.J. Lee ,
Rui Li ,
S. Balakumar ,
Chih-Hang Tung ,
Dong-Zhi Chi  and
Dim-Lee Kwong
Fei Gao
Affiliation:
[email protected], Silicon Nano Device Lab, National university of singapore, Department of ECE, National University of Singapore, Block E4A #02-04 Engineering Drive 3, Singapore 117576, Singapore, N/A, 117576, Singapore
S.J. Lee
Affiliation:
[email protected], Silicon nano device Lab, Department of ECE, National University of Singapore, Block E4A #02-04 Engineering Drive 3, singapore, N/A, 117576, Singapore
Rui Li
Affiliation:
[email protected], Silicon nano device Lab, Department of ECE, National University of Singapore, Block E4A #02-04 Engineering Drive 3, singapore, N/A, 117576, Singapore
S. Balakumar
Affiliation:
[email protected], Institute of Microelectronics Engineering, Singapore, singapore, N/A, 117685, Singapore
Chih-Hang Tung
Affiliation:
[email protected], Institute of Microelectronics Engineering, Singapore, singapore, N/A, 117685, Singapore
Dong-Zhi Chi
Affiliation:
[email protected], Institute of Materials Research Engineering, Singapore, N/A, 117602, Singapore
Dim-Lee Kwong
Affiliation:
[email protected], Institute of Microelectronics Engineering, Singapore, singapore, N/A, 117685, Singapore
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Abstract

We report thin SGOI (Silicon Germanium on Insulator) with 65% Ge concentration p- MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) using Ni-germanosilicide Schottky S/D (source/drain) and HfO2/TaN gate stack integrated with conventional self-aligned top gate process. Unlike high temperature S/D activation needed for conventional transistor, low Ni-germanosilicide S/D formation temperature contributes to the excellent capacitance-voltage characteristic, low gate leakage current and hence, well-behaved transistor performance. In addition, SOI structure suppresses the junction leakage problem, resulting in good agreement between the source current and drain current of the MOSFET.

Keywords

microelectronicsGeSi
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 913: Symposium D – Transistor Scaling – Methods, Materials and Modeling , 2006 , 0913-D01-04
Copyright
Copyright © Materials Research Society 2006

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