No CrossRef data available.
Article contents
Profiling Different Kinds of Generated Defects at Elevated Temperature in Both SiO2 and High-k Dielectrics
Published online by Cambridge University Press: 01 February 2011
Abstract
In this work, the effect of elevated temperature on the generated defects with constant voltage stress (CVS) in SiO2 and SiO2/HfSiO stacks is investigated. Applying Trap Spectroscopy by Charge Injection and Sensing (TSCIS) to 6.5 nm SiO2 layers, different kinds of generated traps are profiled at low and high temperature. Also the Stress-Induced Leakage Current (SILC) spectrum of high-k dielectric stack is different at elevated temperature indicating that degradation and breakdown at high temperature is not equivalent to that at low temperature and therefore, extrapolation of data from high to low T or vice versa is challenging.
Keywords
- Type
- Research Article
- Information
- Copyright
- Copyright © Materials Research Society 2010