The damascene fabrication method and the introduction of low-K dielectricspresent a host of reliability challenges to Cu interconnects andfundamentally change the mechanical stress state of Cu lines. In order tocapture the effect of individual process steps on the stress evolution inthe BEoL (Back End of Line), a process-oriented finite element modeling(FEM) approach was developed. In this model, the complete stress history atany step of BEoL can be simulated as a dual damascene Cu structure isfabricated. The inputs to the model include the temperature profile duringeach process step and materials constants. The modeling results are verifiedin two ways: through wafer-curvature measurement during multiple filmdeposition processes and with X-Ray diffraction to measure the mechanicalstress state of the Cu interconnect lines fabricated using 0.13um CMOStechnology. The Cu line stress evolution is simulated during the process ofmulti-step processing for a dual damascene Cu/low-K structure. It is shownthat the in-plane stress of Cu lines is nearly independent of subsequentprocesses, while the out-of-plane stress increases considerably with thesubsequent process steps.