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Processing Impact on Electrical Properties of Lanthanum Silicate Thin Films

Published online by Cambridge University Press:  01 February 2011

Jesse Stephen Jur ,
Daniel J. Lichtenwalner ,
Naoya Inoue  and
Angus I. Kingon
Jesse Stephen Jur
Affiliation:
[email protected], North Carolina State University, Department of Material Science and Engineering, 1001 Capability Drive, 221 Research Bldg 1 (Campus Box 7919), Raleigh, North Carolina, 27695, United States, 919-515-6154, 919-515-3419
Daniel J. Lichtenwalner
Affiliation:
[email protected], North Carolina State University, Department of Materials Science and Engineering, Raleigh, North Carolina, 27695, United States
Naoya Inoue
Affiliation:
[email protected], System Devices Research Labs, NEC, Sagamihara, Kanagawa, 229-1198, Japan
Angus I. Kingon
Affiliation:
[email protected], North Carolina State University, Department of Materials Science and Engineering, Raleigh, North Carolina, 27695, United States
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Abstract

The consequence of tungsten metal purity on the electrical properties of an annealed MOS gate stack with a lanthanum silicate gate dielectric has been investigated. Optimization of the electrical and physical properties of a device with any given dielectric requires the proper choice of metal gate electrode and capping layer. This study is intended to show the importance of tungsten processing optimization and subsequent effects on the equivalent oxide thickness, fixed charge, and density of interface states of La-Si-O gate dielectric MIS devices. In the experiment, La-Si-O films of physical thickness of 1.6 nm were deposited on a Si substrate, subsequently depositing TaN as the gate electrode and W as a capping layer. A post metallization anneal in flowing nitrogen at 1000°C for short times resulted in widely different measured properties of the MIS devices, dependent on the quality of the tungsten deposited. XRD and SIMS profiles of the gate stacks showed a clear relationship between concentration of oxygen and processing of the tungsten. A 1000°C, 10 sec anneal resulted in an EOT change from 1.1 nm to 2.2 nm on gate stacks with low and high oxygen concentration in the tungsten, respectively. Defect densities decreased with increased anneal temperature and time, and annealing with low oxygen-concentration tungsten resulted in higher effective fixed charge. SIMS data suggests that oxygen in the tungsten diffuses to the Si/La-Si-O interface through the TaN electrode, resulting in the observed differences in the defect densities and EOT.

Keywords

dielectricelectrical propertiesannealing
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 917: Symposium E – Gate Stack Scaling – Materials Selection, Role of Interfaces, and Reliability Implications , 2006 , 0917-E10-03
Copyright
Copyright © Materials Research Society 2006

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