Metal silicides have been used extensively in CMOS technology for reducing electrical resistance. As wafer-scale features have shrunk to the sub-half micron domain, obtaining a self-aligned silicide - or salicide - process that satisfies all requirements has become a significant challenge. One part of this challenge lies in developing the necessary scientific insights and technological innovations for the actual salicide process, while the other part lies in building a complete salicide process module which meets requirements of performance, reliability, ease of integration, control, etc. at the least possible cost and cycle-time for technology development. This second part is seldom addressed by researchers, and yet, is fundamentally important for successful application of any salicide technology to actual integrated circuit products. This paper presents a complete picture of the salicide module in the context of all the aforesaid components; and describes the use of abstraction and hierarchical models to capture process information and to facilitate process design. Prototype compact models for key wafer-state and performance outputs such as TiSi2 thickness and resistance are presented to demonstrate implementation of this process module.