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Process Integration of Composite High-k Tunneling Dielectric for Nanocrystal Based Carbon Nanotube Memory

Published online by Cambridge University Press:  01 February 2011

Udayan Ganguly ,
Tuo-Hung Hou  and
Edwin Chihchuan Kan
Udayan Ganguly
Affiliation:
[email protected], Applied Materials, Applications Development Center, 974 E Arques Ave B81, Sunnyvale, CA, 94085, United States, 614-598-2339, 408-584-1194
Tuo-Hung Hou
Affiliation:
[email protected], Cornell University, Electrical and Computer Engr, 323 Phillips Hall Cornell University, Ithaca, NY, 14853, United States
Edwin Chihchuan Kan
Affiliation:
[email protected], Cornell University, Electrical and Computer Engr, 404 Phillips Hall Cornell University, Ithaca, NY, 14853, United States
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Abstract

Recently, metal nanocrystal based carbon nanotube memory has been demonstrated with sub-5V low bias programming, single electron sensitivity but poor room temperature retention. The process integration of an ultra-thin tunnel dielectric is essential for lateral, vertical scaling and reliable room temperature operation. Low defect density and conformal deposition on the nanotube are required to enhance the performance as a tunnel barrier. Additionally, Au contamination in the CNT decreases the on/off current ratio in the CNTFETs by substantially increasing the off current. Consequently, the dielectric should function as a good diffusion barrier for Au in the nanocrystals. We have explored composite tunneling dielectric film with SiO2 seed layer for conformal high-k deposition to demonstrate minimal Au contamination and improved retention. Room temperature retention of better than three days has been observed.

Keywords

memorynanoscaledielectric
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 961: Symposium O – Nanostructured and Patterned Materials for Information Storage , 2006 , 0961-O05-12
Copyright
Copyright © Materials Research Society 2007

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