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A Predictive Model for Controlling Wafer Level Polish Rate Uniformity in Oxide CMP

Published online by Cambridge University Press:  01 February 2011

Tushar P. Merchant ,
Leonard J. Borucki ,
A. Scott Lawing ,
Suman K. Banerjee  and
John N. Zabasajja
Tushar P. Merchant
Affiliation:
Technology Solutions, Freescale Semiconductor Inc., MD: EL722, Tempe, AZ-85284, U.S.A.
Leonard J. Borucki
Affiliation:
Technology Solutions, Freescale Semiconductor Inc., MD: EL722, Tempe, AZ-85284, U.S.A. Intelligent Planar, 3831 E. Ivy St., Mesa, AZ-85205, U.S.A.
A. Scott Lawing
Affiliation:
Technology Solutions, Freescale Semiconductor Inc., MD: EL722, Tempe, AZ-85284, U.S.A. Rohm and Haas Electronic Materials, 3804 E. Watkins St., Phoenix, AZ-85034, U.S.A.
Suman K. Banerjee
Affiliation:
Technology Solutions, Freescale Semiconductor Inc., MD: EL722, Tempe, AZ-85284, U.S.A.
John N. Zabasajja
Affiliation:
Technology Solutions, Freescale Semiconductor Inc., MD: EL722, Tempe, AZ-85284, U.S.A.
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Abstract

A stress based engineering model has been developed that predicts the removal rate profile across the wafer as a function of the principal and shear stresses on the wafer. The model reproduces the form of the radial variation in polish rate that is seen without back side air for the current set of consumable conditions and the changes in the polish rate profile that occur when back side air pressure is used on an IPEC-472 tool. The model which is GUI based and can be run in the fab, returns the optimum recipe setting to maximize polish rate uniformity based on the current tool performance. Implementing this model in production resulted in a 50% improvement in within wafer uniformity statistics.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 867: Symposium W – Chemical-Mechanical Planarization-Integration, Technology and Reliability , 2005 , W5.3
Copyright
Copyright © Materials Research Society 2005

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