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Optimization of Stressor Layers Created by ClusterCarbon™ Implantation

Published online by Cambridge University Press:  01 February 2011

Karuppanan Sekar
Affiliation:
[email protected], SemEquip Inc, Process Technology, 34 Sullivan Rd, North Billerica, MA, 01862, United States, 978-262-3628, 978-262-0950
Wade A Krull
Affiliation:
[email protected], SemEquip Inc, Process Technology, 34 Sullivan Rd, North Billerica, MA, 01862, United States
Thomas N Horsky
Affiliation:
[email protected], SemEquip Inc, Technology Group, 34 Sullivan Rd, North Billerica, MA, 01862, United States
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Abstract

Si:C layers are interesting candidates as stressor layers for NMOS transistors. Growth of such a Si:C layer has been realized by an expensive epitaxial growth process for devices to produce tensile strain in the channel, leading to enhanced mobility and device performance. Use of a monomer carbon ion implant in conjunction with a Ge pre-amorphizing implant (Ge-PAI) in Si is an alternative, lower cost approach to obtaining such SiC layers. This approach has not yielded desired device performance owing to low carbon substitutionality [C]sub, and also the presence of end-of-range (EOR) defects and large leakage currents due to the Ge-PAI implant. In this study we will show the formation of a Si:C layer using a ClusterCarbon approach that creates self-amorphization in Si thus avoiding an extra Ge-PAI implant step. We show that more than 2% substitutional carbon can be realized by using solid-phase-epitaxial-regrowth (SPER) and millisecond anneal. Si:C layers are characterized by using High Resolution X-ray Diffraction (HRXRD) and SIMS techniques.

Type
Research Article
Copyright
Copyright © Materials Research Society 2008

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References

REFERENCES

1.) Chui, King-Jien, Ang, Kah-Wee, Balasubramanian, Narayanan, Li, Ming-Fu, Samudra, Ganesh S. and Leo, Yee-Chia, IEEE Transactions of Electron Devices, 54, 249 (2007)Google Scholar
2.) Li-Fatou, A. et al, Proceeding of the Electro-chemical Society Meeting, 212, 1305 (2007)Google Scholar
3.) Gyulai, J. and Revesz, P., Conf. Serv.-Inst. Phys., 46, 128 (1979)Google Scholar
4.) Liu, Y. et al, Symposium on VLSI Technology Digest of Technical Papers, 44 (2007)Google Scholar
5.) Picraux, S. T., Ann. Rev. Mater. Sci. 14, 335 (1984)Google Scholar
6.) Kramer, K. M. and Thompson, M. O., J. Appl. Phys. 79, 4118 (1996)Google Scholar
7.) Melendez-Lira, et al, J. App. Phys. 82, 4246 (1997)Google Scholar
8.) Sekar, K., et al, Proc. International Workshop on INSIGHT in Semiconductors Device Fabrication, Metrology and Modeling, 141 (2007)Google Scholar
9.) Hornstra, J. and Bartels, W. J., J. Cryst. Growth, 44, 513 (1978); M. Berti et al, J. Appl. Phys. 72, xx (1998)Google Scholar
10.) Goorsky, M. S. et al, Appl. Phys. Lett. 60, 2758 (1992); J. W. Stane et al, J. Appl. Phys. 76, 3656 (1994)Google Scholar