A new method for non-destructive, small area characterization of ultra-shallow junctions, called Carrier Illumination™ (CI) has recently been developed. This work validates the CI measurement in full CMOS and NMOS process flows, with the aim of demonstrating its capability to provide in-line characterization of junction depth and uniformity on product wafers. Measurements have been carried out on both unpatterned and patterned wafers at various steps in the SEMATECH standard process flow. CI was used to characterize annealed 800 eV B11 PLDD implants into n-wells and annealed As75 NLDD source/drain (S/D) implants into p-wells. This work demonstrates correlation to dose, junction depth as measured with SIMS and SRP, and electrical properties of test structures.

(1) Proceedings of the Fifth International Workshop on Measurement, Characterization and Modeling of Ultra-Shallow Doping Profiles in Semiconductors, usj-99, Research Triangle Park, NC, March 1999, pp. 314-18.