Hostname: page-component-586b7cd67f-dlnhk Total loading time: 0 Render date: 2024-11-25T15:35:10.547Z Has data issue: false hasContentIssue false

A new vertical nanoporous functional structure process fabrication to control one dimensional nanostructure growth

Published online by Cambridge University Press:  19 April 2012

Emmanuel Lefeuvre
Affiliation:
LPICM – Ecole Polytechnique Route de Saclay, 91128 PALAISEAU
Ki-Hwan Kim
Affiliation:
LPICM – Ecole Polytechnique Route de Saclay, 91128 PALAISEAU
Marc Châtelet
Affiliation:
LPICM – Ecole Polytechnique Route de Saclay, 91128 PALAISEAU
Costel-Sorin Cojocaru
Affiliation:
LPICM – Ecole Polytechnique Route de Saclay, 91128 PALAISEAU
Get access

Abstract

A novel vertical nanoporous structure is reported as a starting point for the fabrication of a fully-surround gate field effect transistor (FET) based on well-ordered nanostructures array. The proposed porous stacking is perfectly suited both for the collective organization of high density (up to 1011.cm-2) arrays of nanostructures like nanowires (NWs) or nanotubes (NTs), as with calibrated diameters (during growth), as well as for easing the Source, Gate, and Drain electrodes connections for individual or groups of nanostructures. Moreover the unique fully-surround gate architecture enables a quasi-ideal coupling between the gate and the channel, theoretically leading to improved devices performance and reduced global power consumption.

In this paper we describe the main steps for this versatile and lithography-free technique to fabricate a multi-layer porous template down to the nanometer scale, as well as the first nanostructures (carbon NTs) growth attempts inside such functional template. We highlight the fact that the proposed porous structure may acts as a passive template for the one-dimensional nanomaterials growth as well as an active element in the future device.

The proposed approach is in line with bottom-up fabrication approach to provide smaller devices, and is fully-compatible with classical processes used in the silicon industry.

Type
Research Article
Copyright
Copyright © Materials Research Society 2012

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

[1] de Luna Bugallo, A., et al. ., « Visible-blind photodetector based on p–i–n junction GaN nanowire ensembles », Nanotechnology, vol. 21, no. 31, p. 315201, août 2010.Google Scholar
[2] Soci, C. et al. ., « ZnO Nanowire UV Photodetectors with High Internal Gain », Nano Lett., vol. 7, no. 4, p. 10031009, oct. 2011.Google Scholar
[3] Quitoriano, N. J. et Kamins, T. I., « Integratable Nanowire Transistors », Nano Lett., vol. 8, no. 12, p. 44104414, oct. 2011.Google Scholar
[4] Cohen, G. M. et al. ., « Nanowire metal-oxide-semiconductor field effect transistor with doped epitaxial contacts for source and drain », Applied Physics Letters, vol. 90, no. 23, p. 233110, 2007.Google Scholar
[5] Kelzenberg, M. D. et al. ., « Enhanced absorption and carrier collection in Si wire arrays for photovoltaic applications », Nat Mater, vol. 9, no. 3, p. 239244, mars 2010.Google Scholar
[6] Tian, B. et al. ., « Coaxial silicon nanowires as solar cells and nanoelectronic power sources », Nature, vol. 449, no. 7164, p. 885889, oct. 2007.Google Scholar
[7] Zhou, X., « Silicon nanowires as chemical sensors », Chemical Physics Letters, vol. 369, no. 1-2, p. 220224, févr. 2003.Google Scholar
[8] Duan, X. et al. ., « High-performance thin-film transistors using semiconductor nanowires and nanoribbons », Nature, vol. 425, no. 6955, p. 274278, 2003.Google Scholar
[9] Huang, J., Tao, A. R., Connor, S., He, R., et Yang, P., « A General Method for Assembling Single Colloidal Particle Lines », Nano Lett., vol. 6, no. 3, p. 524529, oct. 2011.Google Scholar
[10] Goldberger, J., Hochbaum, A. I., Fan, R., et Yang, P., « Silicon Vertically Integrated Nanowire Field Effect Transistors », Nano Lett., vol. 6, no. 5, p. 973977, oct. 2006.Google Scholar
[11] Cui, Y., Björk, M. T., Liddle, J. A., Sönnichsen, C., Boussert, B., et Alivisatos, A. P., « Integration of Colloidal Nanocrystals into Lithographically Patterned Devices », Nano Lett., vol. 4, no. 6, p. 10931098, oct. 2011.Google Scholar
[12] Park, Jong-Tae et Colinge, J.-P., « Multiple-gate SOI MOSFETs: device design guidelines », Electron Devices, IEEE Transactions on, vol. 49, no. 12, p. 22222229, 2002.Google Scholar
[13] Gnani, E., Reggiani, S., Rudan, M., et Baccarani, G., « Design Considerations and Comparative Investigation of Ultra-Thin SOI, Double-Gate and Cylindrical Nanowire FETs », in Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European, 2006, p. 371374.Google Scholar
[14] Doyle, B. et al. ., « Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout », in VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, 2003, p. 133134.Google Scholar
[15] Sato, S. et al. ., « Electrical characterization of Si nanowire field-effect transistors with semi gate-around structure suitable for integration », Solid-State Electronics, vol. 54, p. 925928, 2010.Google Scholar
[16] Pribat, D. et Cojocaru, C. S., « Structure De Transistor Vertical Et Procede De Fabrication », 07-févr-2006. [Online]. Available: http://www.directorypatent.com/FR/FR2897204.html. [Accessed: 02-nov-2011].Google Scholar
[17] Lefeuvre, E. et al. ., « Well organized Si nanowires arrays synthesis for electronic devices », presented at the SPIE Optics+Photonics conference, San Diego, California, USA, 2010, p. 776105-776105-6.Google Scholar
[18] Masuda, H. et Fukuda, K., « Ordered Metal Nanohole Arrays Made by a Two-Step Replication of Honeycomb Structures of Anodic Alumina », Science, vol. 268, no. 5216, p. 14661468, juin 1995.Google Scholar
[19] Marquardt, B. et al. ., « Density control of electrodeposited Ni nanoparticles/nanowires inside porous anodic alumina templates by an exponential anodization voltage decrease », Nanotechnology, vol. 19, p. 405607, oct. 2008.Google Scholar
[20] Lefeuvre, E. et al. ., « Optimization of organized silicon nanowires growth inside porous anodic alumina template using hot wire chemical vapor deposition process », Thin Solid Films, vol. 519, no. 14, p. 46034608, mai 2011.Google Scholar
[21] Marquardt, B., « Organisation nanométrique de composant (nanotubes de carbone) utilisant des membranes verticales d’alumine anodique poreuse », 17-déc-2009. [Online]. Available: http://tel.archives-ouvertes.fr/index.php?halsid=pjkpepq00t6oqf5pbns4tj48j3&view_this_doc=pastel-00005877&version=1. [Accessed: 25-oct-2011].Google Scholar
[22] Williams, K. R. et Muller, R. S., « Etch rates for micromachining processing », Microelectromechanical Systems, Journal of, vol. 5, no. 4, p. 256269, 1996.Google Scholar
[23] Laermer, F. et Schilp, A., « Method for anisotropic plasma etching of substrates », 03-déc-1996.Google Scholar
[24] Arbiol, J., Kalache, B., i Cabarrocas, P. R., Morante, J. R., et i Morral, A. F., « Influence of Cu as a catalyst on the properties of silicon nanowires synthesized by the vapour–solid–solid mechanism », Nanotechnology, vol. 18, no. 30, p. 305606, août 2007.Google Scholar
[25] Zhang, Z., Shimizu, T., Chen, L., Senz, S., et Gösele, U., « Bottom‐Imprint Method for VSS Growth of Epitaxial Silicon Nanowire Arrays with an Aluminium Catalyst », Advanced Materials, vol. 21, no. 46, p. 47014705, déc. 2009.Google Scholar
[26] Nielsch, K., Müller, F., ‐P Li, A., et Gösele, U., « Uniform Nickel Deposition into Ordered Alumina Pores by Pulsed Electrodeposition », Advanced Materials, vol. 12, no. 8, p. 582586, avr. 2000.Google Scholar
[27] Kim, K.-H., Lefeuvre, E., Châtelet, M., Pribat, D., et Cojocaru, C. S., « Laterally organized carbon nanotube arrays based on hot-filament chemical vapor deposition », Thin Solid Films, vol. 519, no. 14, p. 45984602, mai 2011.Google Scholar