We have established a correlation between contact resistance, measured on VLSI MOS integrated circuits at final electrical test, with thermal wave modulated reflectance signal measured just after the metal contact hole etch process. This correlation exists because etching past the time that a particular contact hole is cleared of oxide (i.e., overetching) causes (a) a thinning of the underlying shallow ion-implanted low-resistivity silicon layer with a resulting increase in the contact resistance, and (b) damage to the silicon. Damape was measured on the actual product wafers with the thermal wave modulated reflectance method employing low-power laser beams in a noncontact, nondestructive manner. Hence, the thermal wave measurements of damage make it possible to monitor the etch processing on the product wafers.

Our results show monotonic increases in both the damage (mod. reflec. from 30 to 260 units) and contact resistance (from 40 to 180 ohms/contact) with overetch time up to 1.5 min., at which point polymer deposition alters the dependence by screening the silicon surface. We show results obtained for three categories of VLSI devices (SRAM, PROM, FIFO), and report on the advantages and limitations of this new method for realtime plasma etch inspection.