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Negative Bias Temperature Instability for P-channel of LTPS Thin Film Transistors with Fluorine Implantation

Published online by Cambridge University Press:  01 February 2011

Chyuan-Haur Kao  and
W. H. Sung
Chyuan-Haur Kao
Affiliation:
[email protected], Chang Gung University, Electronics Engineering, 259 Wen-Hwa 1st Road, Kwei-Shan, Tao-Yuan, 333, Taiwan, +886-3-2118800-5783, +886-3-2118507
W. H. Sung
Affiliation:
Chang Gung University, Electronics Engineering, 259 Wen-Hwa 1st Road, Kwei-Shan, Tao-Yuan, 333, Taiwan
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Abstract

This paper studies the impact of LTPS (low temperature polycrystalline silicon) TFTs with fluorine implantation under NBTI (Negative bias temperature instability) stress. The fluorinated TFTs' devices can obtain better characteristics with samller threshold voltage shift, lower trap states and lower subthreshold swing variation. Therefore, the fluorine implantation does not only improve initial electrical characteristics, but also suppresses the NBTI-induced degradation.

Keywords

amorphouselectrical propertiesplasma-enhanced CVD (PECVD) (deposition)
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1066: Symposium A – Amorphous and Polycrystalline Thin-Film Silicon Science and Technology—2008 , 2008 , 1066-A16-03
Copyright
Copyright © Materials Research Society 2008

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References

REFERENCES

[1] Yoneda, K. Yokoyama, R. Yamada, T.: Symp. VLSI Circuits, Tech. Dig., 2001, p. 85.Google Scholar
[2] Serikawa, T. Shirai, S. Okamoto, A. and Suyama, S.: IEEE Trans. Electron Devices 36, 1929 (1989).Google Scholar
[3] Wu, I. W. Jackson, W. B. Huang, T. Y. Lewis, A. G. and Chiang, A.: IEEE Electron Device Lett. 11, 167 (1990).Google Scholar
[4] Blat, C. E. Nicollian, E. H. and Poindexter, E. H.: J. Appl. Phys. 63 (1991) 1712.Google Scholar
[5] Schroder, D. K. and Babcock, J. A.: J. Appl. Phys. 94, 1 (2003).Google Scholar
[6] Krishnan, A. T. Reddy, V. and Krishnan, S.: IEDM Tech. Dig., 2001, p. 865.Google Scholar
[7] Maeda, S. Maegawa, S. Ipposhi, T. Nishimura, H. Ichiki, T. Mitsuhashi, J. Ashida, M. Muragishi, T. and Nishimura, T.: VLSI Symp. Tech. Dig., 1993, p. 29–30.Google Scholar
[8] Okuyama, K. Kubota, K. Hashimoto, T. Ikeda, S. and Koike, A.: IEDM Tech. Dig., 1993, p. 527.Google Scholar
[9] Chen, Chih-Yang, Lee, Jam-Wem, Chen, Wei-Cheng, Lin, Hsiao-Yi, Yeh, Kuan-Lin, Lee, Po-Hao, Wang, Shen-De, and Lei, Tan-Fu: IEEE Electron Device Lett. 27, 893 (2006).Google Scholar
[10] Chen, Chih-Yang, Lee, Jam-Wem, Wang, Shen-De, Shieh, Ming-Shan, Lee, Po-Hao, Chen, Wei-Cheng, Lin, Hsiao-Yi, Yeh, Kuan-Lin, Lee, Po-Hao, and Lei, Tan-Fu: IEEE. Trans. Electron Devices 53, 2993 (2006).Google Scholar
[11] Kao, Chyuan Haur, Lai, C. S. and Lee, C. L.: Journal of Electrochemical Society 154, 259 (2007).Google Scholar