The purpose of this work was to investigate integration of aluminum multi-level damascene devices with the CMP module. Traditionally aluminum is used in the Metal-1 level of device manufacturing and Reverse Ion Etching (RIE) is used to remove the aluminum over layer. However for <0.25-µproportional]m device rules RIE is not a method of choice due to incomplete removal of the over layer leaving stringers that cause shorting, as well as poor With-In Wafer NonUniformity (WIWNU). The result is loss of device yield and process problems for BEOL modules. Integrating aluminum device wafers into the CMP module has its own drawbacks such as immature consumables, i.e., slurry and polishing pads, as well as ease of scratching the soft aluminum interconnect structures. Hence the basis of this work is to highlight the main issues that impede the integration of the aluminum CMP process. Specifically we investigated the origin of deep aluminum scratches and the effect of not completely removing the residue barrier material, which can cause shorting and poor electrical performance. It is argued in this work that the observed deep scratches in the aluminum material are due to the polished debris emanating from the titanium glue layer. Recommendations are made to help to reduce this effect by design modification to the die layout on the patterned wafer and using electrical testing methods to help ascertain the minimum Over Polishing (OP) time required in order to ensure maximum die yield.