In recent years the growth of virtual substrates using graded SiGe buffer layers has shown great promise for the development of high performance devices. Whilst significant progress has been made in the control of growth conditions to produce low threading dislocation densities of the order suitable for commercial exploitation, several technological problems still have to be overcome. An example of such problems are cosmetic surface defects such as pits and the cross hatched surface roughness associated with mosaic crystal tilts. The work described here utilises a variety of techniques, including X-ray diffraction reciprocal space maps, TEM, AFM and SIMS to provide a comparison between several SiGe virtual substrates grown using low pressure-CVD at high (≈800°C) and low (≈6000°C) temperatures, and at different grade rates (5–50% Ge μm−1). The growth conditions are seen to have a strong effect on the crystal tilts present in the layers with the low temperature layers showing a much larger spread of mosaic tilts. The origin of these tilts is seen to occur during the early stages of the relaxation process irrespective of growth temperature and at similar Ge fractions for all samples. TEM imaging close to the initial growth interface shows that dislocation pileups occur in this region and also suggest that the pileups have a characteristic spacing of 1–2μm. A similar characteristic length scale is also observed in the surface roughness by AFM, the form of which is seen to depend upon the growth conditions.