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Modeling and Simulation of Parasitic Effects in Stacked Silicon

Published online by Cambridge University Press:  26 February 2011

Gunter Elst
Gunter Elst*
Affiliation:
[email protected], Fraunhofer IIS, Design Automation, Zeunerstrasse 38, Dresden, 01069, Germany
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Abstract

Devices and interconnect structures of new semiconductor and packaging technologies show parasitic physical effects with a growing influences of the system behavior. Therefore, the design technology has to be developed and adjusted to ensure high system performance and reliability of these very complex systems on chip and in a stack. The influences of parasitic effects on the circuit behavior have to be minimized within the design process.

Typical parasitic effects of the Vertical System Integration (VSI®) by stacked silicon are discussed in this paper. Effects like electro thermal coupling, electromagnetic interactions, and the sensitivity due to parameter variations and their influence to the system behavior are identified and modeled. Approaches for minimization of these influences by design modifications are presented.

Keywords

microelectronicssimulationthermoelectricity
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y02-02
Copyright
Copyright © Materials Research Society 2007

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References

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