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Manufacturability Issues for Application of Silicides In 0.25 μm CMOS Process and Beyond

Published online by Cambridge University Press:  15 February 2011

Q. F. Wang ,
A. Lauwers ,
F. Jonckx ,
M. de Potter ,
Chun-Cho Chen  and
K. Maex
Q. F. Wang
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
A. Lauwers
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
F. Jonckx
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
M. de Potter
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Chun-Cho Chen
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
K. Maex
Affiliation:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
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Abstract

Key issues associated with the self-aligned silicide technology, such as formation of silicides on narrow poly gate, shallow silicided junction formation, gate to source/drain bridging, and interface contact resistance, are discussed. The comparison of important technological aspects for TiSi2 and CoSi2 is presented. The emphasis of this work is focused on the CoSi2 salicide technology with different variations, namely conventional process, Co/Ti capping process, and Ti/Co process. Based on the experimental results, CoSi2 should be considered as an attractive alternative to TiSi2 for the applications in sub-0.25 μm ULSI integrated circuits.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 402: Symposium H – Silicide Thin Films-Fabrication, Properties and Applications , 1995 , 221
Copyright
Copyright © Materials Research Society 1996

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