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A Low-Temperature Process for Device Quality Si/SiO2 Interfaces on Si(111)

Published online by Cambridge University Press:  21 February 2011

T. Yasuda ,
D. R. Lee ,
C. H. Bjorkman ,
Y. Ma ,
G. Lucovsky ,
U. Emmerichs ,
C. Meyer ,
K. Leo  and
H. Kurz
T. Yasuda
Affiliation:
Departments of Physics, Materials Science and Engineering, and Electrical and Computer EngineeringNorth Carolina State University, Raleigh, NC 27695-8202
D. R. Lee
Affiliation:
Departments of Physics, Materials Science and Engineering, and Electrical and Computer EngineeringNorth Carolina State University, Raleigh, NC 27695-8202
C. H. Bjorkman
Affiliation:
Departments of Physics, Materials Science and Engineering, and Electrical and Computer EngineeringNorth Carolina State University, Raleigh, NC 27695-8202
Y. Ma
Affiliation:
Departments of Physics, Materials Science and Engineering, and Electrical and Computer EngineeringNorth Carolina State University, Raleigh, NC 27695-8202
G. Lucovsky
Affiliation:
Departments of Physics, Materials Science and Engineering, and Electrical and Computer EngineeringNorth Carolina State University, Raleigh, NC 27695-8202
U. Emmerichs
Affiliation:
Institute of Semiconductor Electronics II, Rheinisch-Westfalishe Technische Hochschule, 5100 Aachen, Germany
C. Meyer
Affiliation:
Institute of Semiconductor Electronics II, Rheinisch-Westfalishe Technische Hochschule, 5100 Aachen, Germany
K. Leo
Affiliation:
Institute of Semiconductor Electronics II, Rheinisch-Westfalishe Technische Hochschule, 5100 Aachen, Germany
H. Kurz
Affiliation:
Institute of Semiconductor Electronics II, Rheinisch-Westfalishe Technische Hochschule, 5100 Aachen, Germany
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Abstract

Device-quality Si/SiO2 interfaces with an interface trap density as low as ∼2 × 1010cm−2 eV−1 were formed on Si( 111) surfaces by a low-temperature, two-step oxidation/deposition process using a remote plasma enhanced CVD system. The micromorphology of the initial Si(1 11) surface was changed i) by controlling the roughness of the initial Si surface through the pH of HF/NH4F treatments, and ii) by an introduction of surface steps using Si(111) wafers that were cut off the axis in the direction. When the Si wafer was subjected to a pre-deposition rinse in a 40 wt-% NH4F solution to develop an atomically smooth surface, the SiO2/Si(111) interface displayed a midgap interface trap density, Dit, of 2∼3 × 1010cm−2 eV−1 with Al as an electrode material. The Dit values increased systematically up to about 1 × 1011cm−2 eV−1 as the pH of the HF/NH4F treatment was decreased. The density of surface steps had a lesser effect on Dit. MOS capacitors with an n-type poly-Si electrode also showed Dit of ∼2 × 1010cm−2 eV−1. The effects of the hightemperature processing associated with poly-Si deposition and doping are discussed in conjunction with our recent study on second harmonic generation from the SiO2/Si interfaces.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 315: Symposium Y – Surface Chemical Cleaning and Passivation for Semiconductor Processing , 1993 , 375
Copyright
Copyright © Materials Research Society 1993

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References

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