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Low Resistivity CoSi2 Surface Layers for Use as Contacts in CMOS Processes

Published online by Cambridge University Press:  28 February 2011

Sarah A. Audet
Affiliation:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, N.J. 07974
Conor S. Rafferty
Affiliation:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, N.J. 07974
Alice E. White
Affiliation:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, N.J. 07974
Ken T. Short
Affiliation:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, N.J. 07974
Yong-Fen Hsieh
Affiliation:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, N.J. 07974
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Abstract

Uniform CoSi2 surface layers 30nm thick have been realized through room temperature implantation of Co+ through a resist or an oxide mask and low temperature (600°C) annealing. TEM studies show that the surface layers are polycrystalline with large, uniformly thick grains. Resistivity values as low as 181µΩ-cm have been obtained. Surface layers of TiSi2 have also been synthesized using a similar process. The ease of formation, the low resistivity and the smooth interfaces of the CoSi2 and TiSi2 surface layers make this technique a promising candidate for contacting source and drain junctions in sub-half-micron CMOS processes.

Type
Research Article
Copyright
Copyright © Materials Research Society 1991

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References

[1] Ng, K.K. and Lynch, W.T., IEEE Trans. on Electr. Dev., ED-34, 503 (1987).Google Scholar
[2] Rubin, L., Hoffman, D., Ma, D. and Herbots, N., IEEE Trans. on Electr. Dev., 37, 183 (1990).Google Scholar
[3] Pfiester, J.R., Mele, T.C., Lib, Y., Jones, R.E., Woo, M., Boeck, B. and Gunderson, C.D., Tech. Dig. IEDM, San Francisco, Dec. 9-12, 1990, 241.Google Scholar
[4] Ditchek, B.M., Journ. of Crystal Growth, 69, 207 (1984).Google Scholar
[5] Parekh, N.S., Roede, H., Bos, A.A., Jonkers, A.G.M. and Verhaar, R.D.V., IEEE Trans. on Electr. Dev., ED-38, 88 (1991).Google Scholar
[6] Hillenius, S.J., Liu, R., Georgiou, G.E., Field, R.L., Wiliams, D.S., Kornblit, A., Boulin, D.M., Johnston, R.L. and Lynch, W.T., Tech. Dig. IEDM, Los Angeles, Dec. 7-10, 1986, 252.Google Scholar
[7] van den Hove, L., Wolters, R., Maex, K., de Keersmaecker, R.F. and Declerck, G.L., IEEE Trans. on Electr. Dev., ED-34, 554 (1987).Google Scholar
[8] Tabasky, M.. Bulat, E.S., Ditchek, B.M., Sullivan, M.A. and Shatas, S.C., IEEE Trans. on Electr. Dev., ED-34, 548 (1987).Google Scholar
[9] Van den Hove, L., Vanhellemont, J., Wolters, R., Claassen, W., DeKeersmaecker, R. and Declerk, G., Solid State Devices, Springer-Verlag, Berlin, 1989, 165.Google Scholar
[10] Liu, R., Williams, D.S. and Lynch, W.T., Journ. of Appl. Phys., 63, 1990 (1988).Google Scholar
[11] Osbum, C.M., Joum. of Electron. Mat., 19, 67 (1990).Google Scholar
[12] Liu, R., Baiocchi, F.A., Heimbrook, L.A., Kovalchick, J., Malm, D.L., Williams, D.S. and Lynch, W.T. in ULSI Science and Technology, edited by Broydo, S. and Osburn, C.M. (Electrohem. Soc. Proc. 87-11, Philadelphia, PA, 1987) pp. 446462.Google Scholar
[13] Tung, R.T., Bean, J.C., Gibson, J.M., Poate, J.M. and Jacobson, D.C., Appl. Phys. Lett., 40, 64 (1987).Google Scholar
[14] White, A.E., Short, K.T., Dynes, R.C., Garno, J.P. and Gibson, J.M., Appl. Phys. Lett., 50, 95 (1987).Google Scholar
[15] Shahidi, G., Davari, B., Taur, Y., Warnock, J., Wordeman, M., Mader, S., McFarland, P., Rodriguez, M., Assenza, R., Bronner, G., Ginzberg, B., Lii, T., Polcari, M. and Ning, T., Tech. Dig. IEDM, San Francisco, Dec. 9-12, 1990, 587.Google Scholar