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Long Time-Constant Trap Effects in Nitride Heterostructure Field Effect Transistors

Published online by Cambridge University Press:  15 March 2011

Xiaozhong Dang
Affiliation:
Department of Electrical and Computer Engineering, University of California at San Diego, 9500 Gilman Drive, La Jolla, CA 92093-0407
Peter M. Asbeck
Affiliation:
Department of Electrical and Computer Engineering, University of California at San Diego, 9500 Gilman Drive, La Jolla, CA 92093-0407
Edward T. Yu
Affiliation:
Department of Electrical and Computer Engineering, University of California at San Diego, 9500 Gilman Drive, La Jolla, CA 92093-0407
Karim S. Boutros
Affiliation:
Epitronics/ATMI, 21002 north 19th Avenue, Suite 5, Phoenix, Arizona 85027-2726
Joan M. Redwing
Affiliation:
Epitronics/ATMI, 21002 north 19th Avenue, Suite 5, Phoenix, Arizona 85027-2726
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Abstract

Current collapse effects in an Al0.25Ga0.75N/GaN HFET have been investigated under pulsed bias conditions, and a detailed investigation of current responses to changes in drain or gate bias voltage (drain-lag and gate-lag, respectively) has been performed. Three components of transient current response to changes in drain and gate bias voltages are distinguished. Surface treatment using KOH etching and the influence of pulsed bias conditions on threshold voltage are investigated to explore the origins of traps associated with each current transient component.

Type
Research Article
Copyright
Copyright © Materials Research Society 2000

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References

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