Hostname: page-component-586b7cd67f-vdxz6 Total loading time: 0 Render date: 2024-11-25T15:27:17.312Z Has data issue: false hasContentIssue false
  • English
  • Français

Interconnection Challenges of the 1990's

Published online by Cambridge University Press:  15 February 2011

Michael A. Fury
Michael A. Fury*
Affiliation:
IBM Corporation Zip 49X, Route 52, Hopewell Junction, NY 12533-6531, (914)894-3248, (914)892-6399, [email protected]
Get access

Abstract

Silicon device performance has improved dramatically over the past two decades. During that time, the portion of total circuit delay attributable to interconnect wiring has increased to nearly half. Changes in the use of aluminum wiring and silicon oxide insulators must be considered to further improve performance.

The generation of ULSI circuitry now under development in the industry depends heavily on innovations in materials and processes to achieve significant improvements in wiring density and circuit performance. The subsequent generation places even greater demands on materials improvements for lower resistivity wiring and a lower dielectric constant insulator. Integrating materials and methods compatible with semiconductor processing while ensuring device reliability will create a significant financial challenge in addition to the technical challenge.

This presentation enumerates the interconnection challenges facing the materials scientist and the circuit designer. The ultimate limits in materials improvements are predictable and finite. Further improvements will be derived from design innovations such as treating interconnects as active rather than passive devices. Accurate physical modelling of MLM structures will complement even more complex electrical modelling. Manufacturing sciences will grow in sophistication if implementation is to succeed. The financial burden of these technical challenges will foster collaborations among semiconductor manufacturers, equipment vendors, and research universities.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 265: Symposium H – Materials Reliability in Microelectronics II , 1992 , 145
Copyright
Copyright © Materials Research Society 1992

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Davidson, E., “Delay Factors for Mainframe Computers,” IEEE 1991 Bipolar Circuits and Technology Meeting, September 9–10, 116 (1991).Google Scholar
2. Edelstein, D.C., “3-D Capacitance Modeling of Advanced Multilayer Interconnection Technologies,” SPIE International Conference on Advances in Interconnection and Packaging, 1389, 352 (1990). In figure 3, Al = Al(Cu)-Ti, SN = Si3N4, Ox = SiO2, PI = polyimide, FP = fluoropolymer, and M = refractory metal etch stop (removed from space between wires).Google Scholar
3. Wilson, S.R., Freeman, J.L. Jr., Tracy, C.J., “A Four-Metal Layer, High Performance Interconnect System for Bipolar and BiCMOS Circuits,” Solid State Technology, November, 67 (1991).Google Scholar
4. Uttecht, R.R., Geffken, R.M., “A Four-Level-Metal Fully Planarized Interconnect Technology for Dense High Performance Logic and SRAM Applications,” VMIC Conference, June 11–12, 20 (1991).Google Scholar
5. Small, M.B., Pearson, D.J., “On-Chip Wiring for VLSI: Status and Directions,” IBM J. Res. Develop. 34(6), 858 (1990).Google Scholar
6. “NTT Develops Multi-Layer Wiring Technique for ICs,” Japan Industrial Journal, December 12, 5 (1991) (0.2 micron via hole technology announced).Google Scholar
7. Patrick, W.J., Guthrie, W.L., Standley, C.L., Schiable, P.M., “Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections,” J. Electrochem. Soc., 138(6), 1778 (1991).Google Scholar
8. Schwartz, G.C., “Planarization Processes for Multilevel Metallization – A Review,” The Electrochemical Society Proceedings of the Symposia on Reliability of Semiconductor Devices and Interconnections and Multilevel Metallization Interconnection, and Contact Technologies, 89(6), 310 (1989).Google Scholar
9. Kaanta, C.W., Bombardier, S.G., Cote, W.J., Hill, W.R., Kerszykowski, G., Landis, H.S., Poindexter, D.J., Pollard, C.W., Ross, G.H., Ryan, J.G., Wolff, S., Cronin, J.E., “Dual Damascene: A ULSI Wiring Technology,” VMIC Conference, June 11–12, 144 (1991).Google Scholar
10. Larabee, G., Chatterjee, P., “DRAM Manufacturing in the '9Os,” Semiconductor International, May, 84 (1991).Google Scholar
11. Levinstein, H.J., “White Paper on IC Fabrication in the Year 2000”, SRC Technical Report T90150, December (1990).Google Scholar
12. Kaufman, F.B., Thompson, D.B., Broadie, R.E., Jaso, M.A., Guthrie, W.L., Pearson, D.J., Small, M.B., “Chemical-Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects,” J. Electrochem. Soc., 138(11), 3460 (1991).Google Scholar
13. Murarka, S.P., “Overview of Copper Technology,” Materials Research Society Conference Proceedings, VLSI VI, 179 (1991).Google Scholar
14. Geffken, R.M., “An Overview of Polyimide Use in Integrated Circuits and Packaging,” The Electrochemical Society 179th Meeting, May 5–10, (1991).Google Scholar
15. Dabral, S., McDonald, J.F., “Design, Fabrication and Evaluation of a Parylene/Cu Test Vehicle,” Current Research, Department of Electrical Engineering, Rensselaer Polytechnic Institute, Troy, NY (unpublished).Google Scholar
16. Seraphim, D.P., Barr, D.E., “Interconnect and Packaging Technology in the 90's,” SPIE International Conference on Advances in Interconnection and Packaging, 1390, 39 (1990).Google Scholar
17. Tummala, R.R., “Electronic Packaging in the 1990's – A Perspective from America,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 14(2), 262 (1991).Google Scholar
18. Wessley, H., Fritz, O., Horn, M., Klimke, P., Koshchnick, W., Schmidt, K.-H., “Electronic Packaging in the 1990's: The Perspective from Europe,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 14(2), 272 (1991).Google Scholar
19. Kaloyeros, A.E., Feng, A., Garhart, J., Holma, M., Brooks, K., Williams, W.S., “The CVD Route to High-Temperature Superconductors,” in Superconductivity and Applications, edited by Kwok, H. (Plenum Press, New York, 1990).Google Scholar
20. Markstein, H., “Optics Evolve as a Viable Interconnection Alternative,” Electronic Packaging and Production, April, 50 (1991).Google Scholar
21. Osinski, M., “Vertical-Cavity Surface-Emitting Semiconductor Lasers for Optical Interconnections,” Proceedings of the First International Workshop on Photonic Networks, Components and Applications, 70 (1991).Google Scholar
22. Chen, R.T., “Optical Interconnects: A Solution to Very High Speed Integrated Circuits and Systems,” SPIE Integrated Optics and Optoelectronics II, 1374, 162 (1990).Google Scholar
23. McDonald, J.F., Vlannes, N.P., Lu, T.-M., Wnek, G.E., Nason, T.C., You, L., “Photonic Multichip Packaging (PMP) using Electro-Optic Organic Materials and Devices,” SPIE International Conference on Advances in Interconnection and Packaging, 1390, 286 (1990).Google Scholar
24. Stambler, I., “Etched Silicon Pillars Glow,” R&D Magazine, September, 22 (1991).Google Scholar
25. Chung, S.H., “Process and Device Simulation Programs Catalog,” Semiconductor Research Corporation Publication #C91200, March (1991).Google Scholar
26. Rebab, K., Sanders, T., Li, Y., “Statistical Design Methodology for Process ” Semiconductor Research Corporation Publication #C91394, May (1991).Google Scholar
27. Green, K.R., Fossum, J.G., “A Pragmatic Approach to Integrated Process/Device/Circuit Simulation for IC Technology Development,” Semiconductor Research Corporation Publication #C91409, May (1991).Google Scholar
28. Ghosh, S.K., Ramkumar, K., Saxena, A.N., “Stress Voiding in Al Interconnects: Effects of interlevel oxide films,” submitted to MRS 1992 Spring Meeting.Google Scholar
29. Saxena, A.N., New York State Sematech Center of Excellence in Multilevel Metallization (unpublished).Google Scholar
30. Hauser, J.R., Rizvi, S.A., “Cluster Tool Technology,” Semiconductor Research Corporation Publication #C91732, September (1991).Google Scholar
31. Davies, J., Dunn, J., “The 90s Decade: Larger Wafers, Cluster Tools and Horizontal Partnering,” Channel, September, 3 (1991).Google Scholar
32. Wise, K.D., Najafi, K., “Microfabrication Techniques for Integrated Sensors and Microsystems,” Semiconductor Research Corporation Publication #C91750, October (1991).Google Scholar
33. Borden, P., “Installing in situ Sensors in Single-Wafer Plasma Etchers,” Microcontamination, February, 43 (1991).Google Scholar
34. Maly, W., Strojwas, A.J., “Pennsylvania Sematech Center of Excellence for Rapid Yield Learning Annual Report,” Semiconductor Research Corporation Technical Report #T91118, August (1991).Google Scholar
35. Holton, W.C., “Precompetitive Cooperative Research: The Culture of the '90s,” SPIE Advanced Techniques for Integrated Circuit Processing, 1392, 27 (1990).Google Scholar