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Integration of fullerenes and carbon nanotubes with aggressively scaled CMOS gate stacks

Published online by Cambridge University Press:  01 February 2011

Udayan Ganguly ,
Chungho Lee  and
Edwin C. Kan
Udayan Ganguly
Affiliation:
Department of Materials Science and Engineering, Cornell University
Chungho Lee
Affiliation:
School of Electrical and Computer Engineering, Cornell University
Edwin C. Kan
Affiliation:
School of Electrical and Computer Engineering, Cornell University
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Abstract

Here we report the first study towards the integration of fullerenes and carbon nanotubes (CNT) in the gate stack of CMOS technology, which is a promising hybrid approach of top-down and bottom-up fabrication process. Prospective processes for C60 and CNT deposition over an aggressively scaled 2 nm gate oxide in the MOS capacitor structure have been monitored. CV measurements show minimal silicon contamination and interface states. Step charging at a specific voltage that corresponds to a fixed number density of C60 is used to establish the structural integrity and size-mono-dispersion of C60. The CV method can be further used to probe the charge injection into C60 and its anions to establish fundamental understanding of their molecular orbital (MO) structure.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 789 , 2003 , N16.3
Copyright
Copyright © Materials Research Society 2004

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References

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