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Integration Challenges for Advanced Salicide Processes and their Impact on CMOS Device Performance

Published online by Cambridge University Press:  14 March 2011

K. Wieczorek ,
M. Horstmann ,
H.-J. Engelmann ,
K. Dittmar ,
W. Blum ,
A. Sultan ,
P. Besser  and
A. Frenkel
K. Wieczorek
Affiliation:
AMD Saxony Manufacturing GmbH, Postfach 110110, D-01330 Dresden, Germany
M. Horstmann
Affiliation:
AMD Saxony Manufacturing GmbH, Postfach 110110, D-01330 Dresden, Germany
H.-J. Engelmann
Affiliation:
AMD Saxony Manufacturing GmbH, Postfach 110110, D-01330 Dresden, Germany
K. Dittmar
Affiliation:
AMD Saxony Manufacturing GmbH, Postfach 110110, D-01330 Dresden, Germany
W. Blum
Affiliation:
AMD Saxony Manufacturing GmbH, Postfach 110110, D-01330 Dresden, Germany
A. Sultan
Affiliation:
AMD-Motorola Logic Alliance, 3501 Ed Bluestein Blvd., Austin, TX 78721
P. Besser
Affiliation:
AMD-Motorola Logic Alliance, 3501 Ed Bluestein Blvd., Austin, TX 78721
A. Frenkel
Affiliation:
AMD-Motorola Logic Alliance, 3501 Ed Bluestein Blvd., Austin, TX 78721
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Abstract

CoSi2 has emerged as the silicide of choice for 0.18μm CMOS technologies and below. Robustness and scaling-performance of an integrated CoSi2-module, however, is shown to critically depend upon careful optimization of each individual process-step. The impact of surface-preparation, capping layer, initial Co-thickness and thermal processing will be discussed. The scalability of an optimized process meeting all major requirements for application to ULSI devices is demonstrated for gate-length down to 60nm.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 611: Symposium C – Gate Stack & Silicide Issues in Silicon Processing , 2000 , C5.1.1
Copyright
Copyright © Materials Research Society 2000

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References

REFERENCES

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