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In-situ TEM Study of Thermally Induced Voids in 180 nm Cu Interconnects

Published online by Cambridge University Press:  26 February 2011

Jin Ho An  and
P.J. Ferreira
Jin Ho An
Affiliation:
[email protected], The University of Texas at Austin, Materials Science and Engineering, Mail Code C2201, Austin, tx, 78712, United States
P.J. Ferreira
Affiliation:
[email protected]
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Abstract

Cu interconnects have decreased in width and are at around 100 nm. A decrease in interconnect width have led to a predominately bamboo structured Cu lines. In Cu interconnects, void formation during high temperature is a reliability issue, and this study looks at the void formation behavior in damascene Cu interconnects with a predominately bamboo microstructure. First, the crystal texture and grain morphology of the Cu interconnects was observed. Then to determine the void formation behavior, in-situ Transmission Electron Microscopy (TEM) was performed. Voids that formed as a result of in-situ heating were analyzed in terms of preferential void formation sites and crystal orientation where voids formed. In bamboo structured lines, voids formed at the triple junction of grain boundary and Cu/diffusion barrier interface. The crystal orientation where voids nucleated was studied to identify diffusion paths during void nucleation and growth.

Keywords

transmission electron microscopy (TEM)Cuthermal stresses
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 907: Symposium MM – In-Situ Electron Microscopy of Materials , 2005 , 0907-MM03-03
Copyright
Copyright © Materials Research Society 2006

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References

[1] The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2003 Google Scholar
[2] Gan, Dongwen, Wang, Guotao, Ho, Paul S., “Effects of Dielectric Material and Linewidth on Thermal Stresses of Cu line Structures”, IITC 2002 p271–273 Google Scholar
[3] An, J.H., Ferreira, P.J., “In Situ TEM Studies of Nanoscale Cu Interconnects Under Thermal Stress”, in Stability of Thin Films and Nanostructures, edited by Vinci, R.P., Schwaiger, R., Karim, A., and Shenoy, V. (Mater. Res. Soc. Symp. Proc. 854E, Warrendale, PA, 2005), U11.13 Google Scholar
[4] Korhonen, M.A., Borgesen, P., Li, Che-Yu, “Mechanisms of Stress-Induced and Electromigration-Induced Damage in Passivated Narrow Metallizations on Rigid Substrates”, MRS Bulleting July (1992) p61–68 Google Scholar
[5] Nucci, J. A., Keller, R.R., Field, D.P., Shacham-Diamand, Y., “Grain Boundary Misorientation Angles and Stress-Induced Voiding in Oxide Passivated Copper Interconnects”, Appl. Phys. Lett. V70 (1997) p1242–1244 Google Scholar
[6] Keller, R.R., Nucci, J.A., Field, D.P., “Local Texture and Grain Boundaries in Voided Copper Interconnecdts”, J. of Electronic Materials, V26 (1997) p996–1001 Google Scholar
[7] Okabayashi, H., “Stress-Induced Void Formation in Metallization for Integrated Circuits”, Materials Science and Engineering R11 (1993) p191–241 Google Scholar