Hostname: page-component-586b7cd67f-dlnhk Total loading time: 0 Render date: 2024-11-23T08:40:41.798Z Has data issue: false hasContentIssue false
  • English
  • Français

Improved Nitridation of GeO2 Interfacial layer for Ge Gate Stack Technology

Published online by Cambridge University Press:  17 July 2013

P. Bhatt ,
K. Chaudhuri ,
P. Maharaja ,
A. Nainani ,
M. Abraham ,
M. Subramaniam ,
U. Ganguly  and
S. Lodha
P. Bhatt
Affiliation:
Center of Excellence in Nanoelectronics, IIT Bombay, Mumbai, India, 400076
K. Chaudhuri
Affiliation:
Center of Excellence in Nanoelectronics, IIT Bombay, Mumbai, India, 400076
P. Maharaja
Affiliation:
Center of Excellence in Nanoelectronics, IIT Bombay, Mumbai, India, 400076
A. Nainani
Affiliation:
Applied Materials, Santa Clara, USA, 94085
M. Abraham
Affiliation:
Applied Materials, Santa Clara, USA, 94085
M. Subramaniam
Affiliation:
Applied Materials, Santa Clara, USA, 94085
U. Ganguly
Affiliation:
Center of Excellence in Nanoelectronics, IIT Bombay, Mumbai, India, 400076
S. Lodha
Affiliation:
Center of Excellence in Nanoelectronics, IIT Bombay, Mumbai, India, 400076
Get access

Abstract

Nitridation of GeO2 interfacial layer (IL) was done using continuous wave (CW) and pulsed wave (PW) decoupled plasma nitridation (DPN) processes. Langmuir probe analysis of the N2 plasma demonstrates that at the same effective power and pressure, PW plasma has similar electron density (Ne) with lower electron temperature (kTe) and plasma potential (Vp) as compared to CW plasma. This results in softer plasma conditions using a PW process leading to lower plasma-related damage in the IL, but without reducing the overall nitrogen concentration. The plasma parameters were further correlated to mobility (μ) and interface trap density (Dit) extracted from fabricated Ge n-MOSFETs. As expected from the plasma analysis, at the same effective power and pressure, the PW DPN process shows 1.2X higher electron mobility as compared to a CW process. This improvement can enable GeON as an IL for future Ge CMOS gate stack technology.

Keywords

Gedielectricx-ray photoelectron spectroscopy (XPS)
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1561: Symposium CC – Gate Stack Technology for End-of-Roadmap Devices in Logic, Power and Memory , 2013 , mrss13-1561-cc04-10
Copyright
Copyright © Materials Research Society 2013 

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

Saraswat, K. C. et al. ., Microelectronics engineering 80, 15 (2005).CrossRefGoogle Scholar
Kutsuki, K. et al. ., Appl. Phys. Lett. 95, 022102 (2009).CrossRefGoogle Scholar
Sugawara, T. et al. ., J. Vac. Sci.Technol.B 24, 2442(2006).CrossRefGoogle Scholar
Chui, Chi On et al. ., IEEE Trans. Electron Dev.53, 1501(2006).CrossRefGoogle Scholar
Tseng, H. H. et al. ., IEEE Electron Device Lett. 23,704(2002).CrossRefGoogle Scholar
Lek, C.M. et al. ., Semicond. Sci. Technol., vol. 17, 2002.CrossRefGoogle Scholar
Chaudhuri, K. et al. ., Booklet of the 43rd IEEE Semiconductor Interface Specialists Conference, San Diego, December 2012.Google Scholar
Veloso, A. et al. ., ESSDERC (2003).Google Scholar
Kuzum, D. et al. ., IEEE Trans.. on Electron Devices, vol. 56, No. 4, Apr. 2009.CrossRefGoogle Scholar
Bersuker, G. et al. ., J. of Appl. Phys., vol. 100, 094108 (2006).CrossRefGoogle Scholar