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Impact of Patterned Layers on Temperature Non-Uniformity during Rapid Thermal Processing for VLSI-Applications

Published online by Cambridge University Press:  25 February 2011

P. Vandenabeele ,
K. Maex  and
R. De Keersmaecker
P. Vandenabeele
Affiliation:
Interuniversity Micro-electronics Center (IMEC v.z.w.)Kapeldreef 75, 3030 Leuven, Belgium
K. Maex
Affiliation:
Interuniversity Micro-electronics Center (IMEC v.z.w.)Kapeldreef 75, 3030 Leuven, Belgium
R. De Keersmaecker
Affiliation:
Interuniversity Micro-electronics Center (IMEC v.z.w.)Kapeldreef 75, 3030 Leuven, Belgium
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Abstract

The influence of patterned oxide layers on temperature non-uniformity during RTP is studied. It is shown that large temperature non-uniformities (up to 80 °C) can occur during RTP as a consequence of large scale patterns of thick oxides. The dependence of oxide thickness and pattern geometry on temperature non-uniformity over a wafer is studied. A set of simulation programs is developed to calculate the optical characteristics of a wafer inside a chamber and to calculate the time dependent temperature non-uniformities on patterned wafers. The calculated results agree very well with the experimental results. The simulation program was used to define the optimal optical conditions for RTP systems for minimal temperature non-uniformity due to patterned overlayers on Si.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 146: Symposium B – Rapid Thermal Annealing/Chemical Vapor Deposition and Integrated Processing , 1989 , 149
Copyright
Copyright © Materials Research Society 1989

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References

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