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The Impact of Fermi Pinning on Thermal Properties of the Instabilities in ZnO TFTs

Published online by Cambridge University Press:  01 February 2011

R.B.M. Cross  and
M. M. De Souza
R.B.M. Cross
Affiliation:
[email protected], De Montfort University, Emerging Technologies Research Centre, The Hawthorne Building,, The Gateway, Leicester LE1 9BH, United Kingdom
M. M. De Souza
Affiliation:
[email protected], De Montfort University, Emerging Technologies Research Centre, The Hawthorne Building,, The Gateway, Leicester, LE1 9BH, United Kingdom
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Abstract

In this paper we describe gate bias and temperature induced device instabilities of inverted-staggered ZnO-TFTs. It is shown that low positive and negative gate bias results in the transfer characteristics shifting in a positive and negative direction respectively. It is suggested that this is a consequence of temporary charge trapping at or close to the channel/insulator interface. The degradation of device parameters such as the threshold voltage, subthreshold slope and effective channel mobility is demonstrated at elevated measurement temperatures, suggesting the generation of defects and/or trap states in the interfacial region. In addition, it is postulated from the extracted activation energy of the drain current that the Fermi-level is pinned during the operation of the devices due to the high level of states close to the conduction band edge. These results highlight the relatively ease with which defects could be created at the interface, indicating a high concentration of weak or strained bonds. Both charge trapping and defect creation-induced instabilities appear to be reversible, as all devices regain their original characteristics after a period of relaxation at room temperature.

Keywords

devicessputteringthin film
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 957: Symposium K – Zinc Oxide and Related Materials , 2006 , 0957-K10-44
Copyright
Copyright © Materials Research Society 2007

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References

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