Hostname: page-component-cd9895bd7-gbm5v Total loading time: 0 Render date: 2024-12-27T01:53:30.890Z Has data issue: false hasContentIssue false

IC Component Level Failure Induced By Intermetallic Layer Structural Defects of Solder Joint

Published online by Cambridge University Press:  11 February 2011

Ming Sun
Affiliation:
ATO-Innovation, Philips Semiconductors San Jose, CA95131, U.S.A.
Mike Loo
Affiliation:
ATO-Innovation, Philips Semiconductors San Jose, CA95131, U.S.A.
Lily Zhao
Affiliation:
ATO-Innovation, Philips Semiconductors San Jose, CA95131, U.S.A.
Get access

Abstract

Solder joint has been widely used in microelectronics industry as an interconnect of Integrated Circuit (IC) chip and Printed Circuit Board (PCB). Frequently, a functional failure of the component on the system is a result of solder joint damage. Eutectic 63Sn/37Pb solder joint mechanical behaviors on Ni/Au plated copper pad and bare copper pad were experimentally investigated to address the effect of pad surface cleanness on the formation of intermetallic compound. The joints with thinner intermetallic compound layer resulted in a poor solder ball shear strength. Microstructural analysis revealed that the oxidations of Ni and Cu during substrate manufacturing contributed to the improper growth of intermetallic compound during assembly and reliability tests. In additions, the experimental results showed that the growth of the intermetallic compound layer were dependent not only on the time and temperature of solder reflow and testing, but also on the cleanness of the pad surfaces and available area for the diffusion of Ni in the case of Ni/Au plated copper pad, Cu in the case of bare copper pad and Sn in the joint area.

Type
Research Article
Copyright
Copyright © Materials Research Society 2003

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1) Lee, W. W., Nguyen, L. T., Selvaduray, G. S., “Solder Joint Fatigue Models: Review and Applicability to Chip Scale Packages,” Microelectronics Reliability, Vol. 40, pp. 231244 (2000).Google Scholar
2) Pang, J. H. L., Hong, K., Shi, X., and Wang, Z. P., “Thermal Cycling Aging Effects on Microstructural and Mechanical Properties of a Single PBGA Solder Joint Specimen,” IEEE Transaction on Components and Packaging Technologies, Vol. 24, No. 1, pp. 1015 (2001).Google Scholar
3) Vianco, P. T., Stephens, J. J., and Rejent, J. A., “Intermetallic Compound Layer Development During the Solid State Thermal Aging of 63Sn-37Pb solder/Au-Pt-Pd Thick Film Couples,” IEEE Transactions on Components, Packaging, and Manufacturing Technologies-Part A, Vol. 20, No. 4, pp. 478490 (1997).Google Scholar
4) Ho, C. E., Tsai, S. Y., and Kao, C. R., “Reaction of Solder with Ni/Au Metallization for Electronic Packages During Reflow Soldering,” IEEE Transactions on Advanced Packaging, Vol. 24, No. 4, pp. 493498 (2001).Google Scholar
5) Zribi, A., Chromik, R. R., Presthus, R., Teed, K., Zavalij, L., DeVita, J., Tova, J., Cotts, E. J., Clum, J. A., Erich, R., Primavera, A., Westby, G., Coyle, R. J., and Wenger, G. M., “Solder Metallization Interdiffusion in Microelectronic Interconnects,” IEEE Transactions on Components and Packaging Technologies, Vol. 23, No. 2, pp. 383387 (2000).Google Scholar
6) Loo, M., Sun, M., Dandia, S., Lee, J., Sharpe, G., and Sumagaysay, F., “Component and Board Level Reliability of High Pin Count Flip Chip Packages,” Proceeding of 2001 SMTA International Conference, pp. 375382 (2001).Google Scholar