3D integration promises to reduce system form factor through direct stacking and interconnection of chips made using different technologies, into a single system. In our case, these interconnects consist of small and deep through wafer vias in the form of Cu nails. One of the enabling technologies to achieve 3D stacks, is thinning on carrier. It involves backside grinding and CMP of patterned wafers down to 20 micron, while temporarily glued to a carrier.

Success of grinding on carrier is found to strongly depend on temporary glue layer properties and bonding quality. Voids in between device wafer and carrier of various origins were observed to cause thin wafer delamination and catastrophic breakage when grinding down below 50 micron. By improvements in the bonding process, we eventually enabled uniform bonding, compatible with standard grinding and CMP techniques.

CMP both removes grinding-induced damage and exposes the Cu nails at the thin wafer backside. The developed CMP consists of 2 steps which are optimized to reduce Cu smearing and within-die uniformity. Both are found to correlate with the local Cu nail density variations.