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Gate-All-Around (GAA) Fully Depleted (FD) Cantilever Channel MOSFET with High-k Dielectric and Metal Gate

Published online by Cambridge University Press:  01 February 2011

Sagnik Dey ,
Se-Hoon Lee ,
Sachin V. Joshi ,
Prashant Majhi  and
Sanjay K. Banerjee
Sagnik Dey
Affiliation:
[email protected], University of Texas at Austin, Electrical and Computer Engineering, Microelectronics Research Center,, 10100 Burnet Rd. Bldg, Austin, TX, 78758, United States, 512-471-8658, 512-471-5625
Se-Hoon Lee
Affiliation:
[email protected], University of Texas at Austin, Electrical and Computer Engg, Austin, TX, 78758, United States
Sachin V. Joshi
Affiliation:
[email protected], University of Texas at Austin, Electrical and Computer Engg, Austin, TX, 78758, United States
Prashant Majhi
Affiliation:
[email protected], Sematech, Austin, TX, 78741, United States
Sanjay K. Banerjee
Affiliation:
[email protected], University of Texas at Austin, Electrical and Computer Engg, Austin, TX, 78758, United States
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Abstract

A MOSFET formed by a Si cantilever channel suspended between source/drain “anchors” wrapped all-around by high-κ dielectric and metal gate is demonstrated. The device shows excellent subthreshold characteristics and low leakage currents due to the fully depleted body and the gate-all-around architecture implemented with a high-κ dielectric and metal gate. At the same time this also allows a high drive current due to mobility enhancements arising from volume inversion of the cantilever channel such that a large ION/IOFF is achieved.

Keywords

microelectronicsHfnanoscale
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 995: Symposium G – Extending Moore's Law with Advanced Channel Materials , 2007 , 0995-G05-16
Copyright
Copyright © Materials Research Society 2007

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References

1.The International Technology Roadmap for semiconductors, Emerging Research Devices, 2003.Google Scholar
2. Wann, C. H., Noda, K., Tanaka, T., Yoshida, M., Hu, C., IEEE Trans. Electron Devices, 43, 1742 (1996).Google Scholar
3. Wong, H. S., Frank, D. J., Taur, Y., and Stork, J. M. C., IEEE IEDM Tech. Digest, 17, 747 (1994).Google Scholar
4. Hisamoto, D., Lee, W.C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., King, T.J., Bokor, J., and Hu, C., IEEE Trans. Electron Devices, 47, 2320 (2000).Google Scholar
5. Young, S. J., Young, C. W., Park, J.H., Lee, J.D., Park, B.G., IEEE Trans. Nanotechnology, 5, 186 (2006).Google Scholar
6. Chin, A., Liao, C.C., Lu, C.H., Chen, W.J., Tsai, C., VLSI Tech Dig., 135 (1999).Google Scholar
7. Zhu, W., Han, J.P., Ma, T.P., IEEE Trans. Electron Devices, 51, 98 (2004).Google Scholar
8. Fischetti, M., Neumayer, D., and Carttier, E., J. Appl. Phys., 90, 4587 (2001).Google Scholar
9. Balestra, F., Cristoloveanu, S., Benachir, M., Brini, J., Elewa, T., IEEE Elec Dev Lett., 8, 410 (1987).Google Scholar
10. Quevedo-Lopez, M.A., Krishnan, S.A., Kirsch, D., Li, C.H.J, Sim, J.H., Huffman, C., Peterson, J. J., Lee, B.H., Pant, G., Gnade, B.E., Kim, M.J., Wallace, R.M., Guo, D., Bu, H., Ma, T.P., IEEE IEDM Tech. Digest, 28, 425 (2005).Google Scholar
11. Kizilyalli, I.C., Roy, P.K., Baumanda, F., Huang, R.Y., Hwang, D., Chacon, C., Irwin, R., Ma, Y., Alers, G. VLSI Tech Dig., 216 (1998).Google Scholar
12.Synopsys Inc., Taurus-Device User Guide, Version 2003.06, 2003.Google Scholar
13. Paasch, G and Ubensee, H Phys. Status Solidi. b 113 165–78 (1982).Google Scholar
14. Chen, K., Wann, H. Clement, Dunster, J., Ko, P. K., Hu, C. and Yoshida, M., Solid-State Electronics, 39, 1515 (1996).Google Scholar