Hostname: page-component-cd9895bd7-gvvz8 Total loading time: 0 Render date: 2024-12-27T01:47:29.110Z Has data issue: false hasContentIssue false
  • English
  • Français

From planar to vertical nanowires field-effect transistors

Published online by Cambridge University Press:  13 August 2012

Guillaume Rosaz ,
Bassem Salem ,
Nicolas Pauc ,
Pascal Gentile ,
Priyanka Periwal ,
Alexis Potié ,
Thierry Baron ,
L. Latu-Romain  and
S. David
Guillaume Rosaz
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054 Grenoble, France
Bassem Salem
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
Nicolas Pauc
Affiliation:
CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054 Grenoble, France
Pascal Gentile
Affiliation:
CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054 Grenoble, France
Priyanka Periwal
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
Alexis Potié
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
Thierry Baron
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
L. Latu-Romain
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
S. David
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
Get access

Abstract

The authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.

Keywords

nanostructureelectrical propertiesdevices
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1439: Symposium N/AA – Nanowires and Nanotubes-Synthesis, Properties, Devices, and Energy Applications of One-Dimensional Materials , 2012 , pp. 101 - 107
Copyright
Copyright © Materials Research Society 2012

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

Johnson, J. C., Choi, H.-J., Knutsen, K. P., Schaller, R. D., Yang, P. and Saykally, R. J., Nature Materials, 1 (2002), 106–110 CrossRefGoogle Scholar
Tian, B., Zheng, X., Kempa, T. J., Fang, Y., Yu, N., Yu, G., Huang, J. and Lieber, C. M., Nature Letters, 449 (2007), 885–890 CrossRefGoogle Scholar
Hua, B., Motohisa, J., Kobayashi, Y., Hara, S., and Fukui, T., Nano Letters, 9 (2009), 112–116 CrossRefGoogle Scholar
Ko, H., Zhang, Z., Chueh, Y.-L., Ho, J. C., Lee, J., Fearing, R. S., and Javey, A., Adv. Funct. Mater. 2009, 19, 3098–3102 CrossRefGoogle Scholar
Cui, Y., Duan, X., Hu, J., and Lieber, C. M. J. Phys. Chem. B, 104 (2000), 5213–5216 CrossRefGoogle Scholar
singh, N., Buddharaju, K. D., Manhas, S. K., Agarwal, A., Rustagi, S. C., Lo, G. Q., Balasubramanian, N. and Kwong, D.-L., IEEE Trans. Elec. Dev. 55 (2008) pp. 3107 CrossRefGoogle Scholar
Wagner, R. S., Ellis, W. C., Appl. Phys. Lett. 4 (1964), 89 CrossRefGoogle Scholar
Potié, A., Baron, T., Latu-Romain, L., Rosaz, G., Salem, B., Montès, L., Gentile, P., Kreisel, J. and Roussel, H., J. Appl. Phys., 110 (2011), 024311–024311 CrossRefGoogle Scholar
Yu, G., and Lieber, C. M., Pure Appl. Chem., 82 (2010), 2295–2314 CrossRefGoogle Scholar
Schmidt, V., Riel, H., Senz, S., Karg, S., Riess, W., and Gösele, U., Small, 2 (2006), 85 – 88 CrossRefGoogle Scholar
Yang, B., Buddharaju, K. D., Teo, S. H. G., Singh, N., Lo, G. Q., and Kwong, D. L., IEEE Electron Device Letters, 29 (2008), 791 CrossRefGoogle Scholar
Bryllert, Tomas, Wernersson, Lars-Erik, Fröberg, Linus E., and Samuelson, Lars, IEEE Electron Device Letters, 27 (2006), 323 CrossRefGoogle Scholar
Tanaka, T., Tomioka, K., Hara, S., Motohisa, J., Sano, E. and Fukui, T., Appl. Phys. Exp. 3 (2010) pp. 025003 CrossRefGoogle Scholar
Rosaz, G, Salem, B, Pauc, N, Gentile, P, Potié, A, Solanki, A and Baron, T, Semicond. Sci. Technol. 26 (2011) 085020 CrossRefGoogle Scholar
Rosaz, G., Salem, B., Pauc, N., Gentile, P., Potié, A., Baron, T., Microelectronic Engineering 88 (2011) 3312–3315.CrossRefGoogle Scholar
Rosaz, G., Salem, B., Pauc, N., Gentile, P., Potié, A., Baron, T., Appl. Phys. Lett. 99 (2011), 193107 CrossRefGoogle Scholar
Kang, D., Ko, J.-H., Bae, E., Hyun, J., Park, W., Kim, B.-K., Kim, J.-J. and Lee, C., J. Appl. Phys. 96 (2004), 7574 CrossRefGoogle Scholar
Sze, S. M., Physics of semiconductor devices, 3 rd Ed., Wiley, New York, 2006 CrossRefGoogle Scholar
Lu, W. and Lieber, C. M, J. Phys. D: Appl. Phys. 39 (2006) R387–R406 CrossRefGoogle Scholar
Björk, M. T., Hayden, O., Schmid, H., Riel, H., and Riess, W., Appl. Phys. Lett. 90, (2007) 142110 CrossRefGoogle Scholar