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Formation of Shallow P+ Junctions Using Two-Step Anneals

Published online by Cambridge University Press:  25 February 2011

C.I. Drowley ,
J. Adkisson ,
D. Peters  and
S.-Y. Chiang
C.I. Drowley
Affiliation:
Hewlett-Packard Laboratories, 3500 Deer Creek Road, Palo Alto, CA 94304
J. Adkisson
Affiliation:
Hewlett-Packard Laboratories, 3500 Deer Creek Road, Palo Alto, CA 94304 >Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139
D. Peters
Affiliation:
Hewlett-Packard Laboratories, 3500 Deer Creek Road, Palo Alto, CA 94304
S.-Y. Chiang
Affiliation:
Hewlett-Packard Laboratories, 3500 Deer Creek Road, Palo Alto, CA 94304
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Abstract

Shallow (0.15-0.2 μm deep) p+ junctions have been formed using boron implanted into silicon which was pre-amorphized using a silicon implant. The implants were annealed using a two-step process; initially the wafers were furnace annealed at 600 °C for 100 min., followed by a rapid isothermal anneal (RIA) at 950-1100 °C for 10 sec. For comparison, some wafers were only given a single-step rapid isothermal anneal at 950-1100 °C for 10 sec. The shallowest junctions were formed when the amorphous silicon layer was deeper than the boron implant, because of the suppression of channelling. When the amorphous/crystalline interface was shallower than the tail of the boron implant, some channeling occurred. This channeling tail exhibited an enhanced diffusion during the single-step RIA which was reduced significantly by the two-step anneal. When the amorphous layer was deeper than the boron implant, the single-step and two-step anneals gave identical results.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 35: Symposium A – Energy Beam-Solid Interactions and Transient Thermal Processing/1984 , 1984 , 375
Copyright
Copyright © Materials Research Society 1985

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References

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