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Flash Memory Scaling: From Material Selection to Performance Improvement

Published online by Cambridge University Press:  01 February 2011

Tuo-Hung Hou ,
Jaegoo Lee ,
Jonathan T. Shaw  and
Edwin C. Kan
Tuo-Hung Hou
Affiliation:
[email protected], Cornell University, School of Electrical and Computer Engineering, 325 Phillips Hall, Ithaca, NY, 14853, United States
Jaegoo Lee
Affiliation:
[email protected], Cornell University, School of Electrical and Computer Engineering, Ithaca, NY, 14853, United States
Jonathan T. Shaw
Affiliation:
[email protected], Cornell University, School of Electrical and Computer Engineering, Ithaca, NY, 14853, United States
Edwin C. Kan
Affiliation:
[email protected], Cornell University, School of Electrical and Computer Engineering, Ithaca, NY, 14853, United States
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Abstract

Below the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure. In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm2) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated by the read disturbance, multi-level possibility and noise margin), and P/E time faster (helped by inserting SRAM buffer at system interface). From both theory and experiments, we will compare the advantages and disadvantages in various material choices in view of 3D electrostatics, quantum transport and CMOS process compatibility.

Keywords

memorynanostructuremicroelectronics
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1071: Symposium F – Materials Science and Technology for Nonvolatile Memories , 2008 , 1071-F02-01
Copyright
Copyright © Materials Research Society 2008

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