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Evaluation of Damages and Pore-sealing Capabilities of Oxidizing and Reducing Etch Plasmas for Single and Dual Damascene Patterning of Porous Ultra-Low-k Materials

Published online by Cambridge University Press:  01 February 2011

Emmanuel Ollier ,
Mathieu Clain ,
Robert Fox ,
Philippe Brun  and
Stephane Jullian
Emmanuel Ollier
Affiliation:
[email protected], Philips Semiconductors, Crolles2Alliance, 860, rue Jean Monnet, Crolles, N/A, 38920, France, (33)4.38.92.21.08, (33)4.38.92.21.20
Mathieu Clain
Affiliation:
[email protected], Freescale Semiconductor, Crolles2Alliance, 870, rue Jean Monnet, Crolles, N/A, 38920, France
Robert Fox
Affiliation:
[email protected], Freescale Semiconductor, Crolles2Alliance, 870, rue Jean Monnet, Crolles, N/A, 38920, France
Philippe Brun
Affiliation:
[email protected], CEA - LETI, Crolles2Alliance, 17, rue des Martyrs, Grenoble, N/A, 38054, France
Stephane Jullian
Affiliation:
[email protected], Philips Semiconductors, Crolles2Alliance, 860, rue Jean Monnet, Crolles, N/A, 38920, France
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Abstract

This paper presents the evaluation of oxidizing and reducing plasmas for post etch pore-sealing treatments during patterning of interconnections in a porous Ultra Low-k (ULK) material. Morphological and chemical characterizations as well as electrical results (resistance, capacitance, leakage, yield) are presented for both single and dual-damascene integrations.

Keywords

microelectronicsdielectricelectrical properties
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 914: Symposium F – Materials, Technology and Reliability of Low-k Dielectrics and Copper Interconnects , 2006 , 0914-F04-05
Copyright
Copyright © Materials Research Society 2006

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References

1 Baklanov, M.R., Le, Q.T., Kesters, E., Iacopi, F., Aelst, J. Van, Struyf, H., Boullart, W., Vanhaelemeersh, S. and Maex, K., IITC Proceedings, pp. 187–189 (2004)Google Scholar
2 Arnal, V. et al., ECS Proceedings (ULSI Process Integration), pp. 221–224 (2005)Google Scholar
3 Beyer, G., Satta, A., Schumacher, J., Maex, K., Besling, W., Kipela, O., Sprey, H., and Tempel, G., Microelectron. Eng. 64, 233 (2002)Google Scholar
4 Fox, R. et al., IEDM Technical digest, pp. 87–90 (2005)Google Scholar
5 Posseme, N., David, T., Meiminger, P., Louveau, O., Chevolleau, T., Joubert, O., Louis, D., Diffusion and Defect Data Part B (Solid State Phenomena) V103–104, pp. 337–340 (2005)Google Scholar
6 Hinsinger, O. et al., IEDM Technical Digest, pp.317–320 (2004)Google Scholar
7 Struyf, H., Hendrickx, D., Olmen, J. Van, Iacopi, F., Richard, O., Travaly, Y., Hove, M. Van, Boullart, W. and Vanhaelemeersh, S., IITC Proceedings, pp. 30–32 (2005)Google Scholar