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Erbium-Silicided Source/Drain Junction Formation by Rapid Thermal Annealing Technique for Decananometer-Scale Schottky Barrier Metal-Oxide-Semiconductor Field- Effect Transistors

Published online by Cambridge University Press:  17 March 2011

Moongyu Jang
Affiliation:
Future Technology Research Division, Electronics and Telecommunication Research Institute, Daejon, 305-350, Korea
Yarkyeon Kim
Affiliation:
Future Technology Research Division, Electronics and Telecommunication Research Institute, Daejon, 305-350, Korea
Jaeheon Shin
Affiliation:
Future Technology Research Division, Electronics and Telecommunication Research Institute, Daejon, 305-350, Korea
Kyoungwan Park
Affiliation:
Department of Nano Science and Technology, University of Seoul, Seoul, 130-743, Korea
Seongjae Lee
Affiliation:
Future Technology Research Division, Electronics and Telecommunication Research Institute, Daejon, 305-350, Korea
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Abstract

The stable growth conditions of erbium-silicide on silicon-on-insulator (SOI) are investigated considering annealing temperature, SOI and sputtered erbium thickness. From the sheet resistance measurement, X-ray diffraction and Auger electron spectroscopy analysis, the optimum annealing temperature is determined as 500°C. Also, for the stable growth of erbium- silicide on SOI, the sputtered erbium thickness should be less than 1.5 times of SOI thickness. As the SOI thickness decreases below this critical thickness, erbium-rich region is formed at the erbium-silicide and buried-oxide interface. By applying the optimized erbium-silicide growth conditions, 50-nm-gate-length n-type SB-MOSFET is manufactured, which shows the possible usage of erbium-silicide as the source and drain material in the n-type Schottky barrier MOSFETs for decananometer regime applications.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

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References

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