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Electronic Transport Across Porous/Crystalline Silicon Heterojunctions

Published online by Cambridge University Press:  01 February 2011

Md. N. Islam ,
Sanjay K. Ram  and
Satyendra Kumar
Md. N. Islam
Affiliation:
Department of Physics, Indian Institute of Technology, Kanpur - 208 016, India
Sanjay K. Ram
Affiliation:
Department of Physics, Indian Institute of Technology, Kanpur - 208 016, India
Satyendra Kumar
Affiliation:
Department of Physics, Indian Institute of Technology, Kanpur - 208 016, India
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Abstract

Al/PS junctions are non-rectifying and quasi-linear whereas Al/PS/c-Si junctions are weakly rectifying. The rectifying behavior is due to PS/c-Si heterojunction. The diode ideality factor (n) is about 8 for bias ≤0.5 V (about 50 for bias ≤5 V) at forward bias and nearly 1 for ≤0.5 V at reverse bias. As the temperature decreases, n at both forward and reverse biases increases. Different current transport mechanisms are found to be operating across the PS/c-Si junctions under forward and reverse biases. The barrier height measured from I-V data for ≤0.5 V is higher for forward bias than that for reverse bias. For high reverse biases (>5 V), the reverse current increases slowly following In(I)∝ V1/2 law. I-V results on PS/c-Si junctions are explained by a multi tunneling-recombination model for forward bias while carrier generation-recombination and barrier lowering effects for reverse bias.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 716: Symposium B – Silicon Materials-Processing, Characterization, and Reliability , 2002 , B11.7
Copyright
Copyright © Materials Research Society 2002

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