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Electromigration in VlSI Metallization Test Structures Stressed Over a Range Of DC Pulse Conditions and Frequencies up to 133 MHz

Published online by Cambridge University Press:  15 February 2011

D. W. Malone
Affiliation:
Department of Materials Science and Engineering, University of Florida, Gainesville, FL 32611
R. E. Hummel
Affiliation:
Department of Materials Science and Engineering, University of Florida, Gainesville, FL 32611
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Abstract

Electrical resistance data were gathered from AI(Cu) VLSI metallization test structures during pulsed DC current stressing (15 mA peak) at elevated temperature (200 °C). Duty cycles of 50%, 67%, and 80% were applied at a frequency (repetition rate) of 133 MHz. Also, a duty cycle of 50% was applied at frequencies of 100 KHz, I MHz, and 133 MHz. The resistance-to-starting resistance ratio, R/Ro, was logged over time, and the data were used to extract the median time dependence of the resistance change. This, in effect, reveals the dependence of the median “failure” time on the R/Ro (or ΔR/Ro) criterion. An “enhancement factor” was defined as the ratio of the median “failure” time from a given pulsed test to that from a DC test with the same peak current. A weak dependence of this enhancement factor on R/Ro was found in the range examined. The degree of enhancement corresponds more closely to the average current density prediction than to the on-time prediction, although there is some small variation according to duty cycle and frequency.

Type
Research Article
Copyright
Copyright © Materials Research Society 1996

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