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Electrical modeling and simulation of nanoscale MOS devices with a high-permittivity dielectric gate stack

Published online by Cambridge University Press:  28 July 2011

J.L. Autran ,
D. Munteanu ,
M. Houssa ,
M. Bescond ,
X. Garros  and
C. Leroux
J.L. Autran
Affiliation:
also withInstitut Universitaire de France(IUF) – Corresponding author ([email protected])
D. Munteanu
Affiliation:
Laboratoire Matériaux et Microélectronique de Provence – L2MP (UMR CNRS 6137), Bâtiment IRPHE, BP 146, 49 rue Joliot Curie, F-13384 Marseille Cedex 13, France
M. Houssa
Affiliation:
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
M. Bescond
Affiliation:
Laboratoire Matériaux et Microélectronique de Provence – L2MP (UMR CNRS 6137), Bâtiment IRPHE, BP 146, 49 rue Joliot Curie, F-13384 Marseille Cedex 13, France
X. Garros
Affiliation:
CEA-LETI, 17 avenue des Martyrs, BP 85X, F-30854 Grenoble Cedex 1
C. Leroux
Affiliation:
CEA-LETI, 17 avenue des Martyrs, BP 85X, F-30854 Grenoble Cedex 1
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Abstract

The electrical behavior of decananometer MOS transistors with high-k dielectric gate stack has been investigated using 2D numerical simulation. Two important electrostatic limitations of high-k materials have been analyzed and discussed in this work: i) the gate-fringing field effects which compromise short-channel performance when simultaneously increasing the dielectric constant and its physical thickness and ii) the presence of discrete fixed charges in the gate stack, suspected to be at the origin of the stretch-out of C-V characteristics, that induces 2D potential fluctuations in the structure. In both cases, the resulting degradation of transistor operation and performance is evaluated with a two-dimensional quantum simulation code.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 811: Symposia D/E – Integration of Advanced Micro-and Nanelectronic Devices-Critical Issues and Solutions , 2004 , D6.1
Copyright
Copyright © Materials Research Society 2004

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References

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