Sub-lithographic copper damascene lines were fabricated to investigatealready today the physical phenomena and scaling limits of metallicconductors in the metallization systems of chip generations which arebelieved to be in production 10 years from now and later. Using standardmanufacturing processes and state-of-the-art process tools, includingstandard lithography tools, narrow copper lines were fabricated at theexpense of a relaxed pitch by use of a removable spacer technique. Thesecopper nano interconnects were passivated and subjected to electricalmeasurements. Our results show that continuous down scaling to increasedevice performance will result in an unfavorable increase of the electricalresistivity of copper in stateof-the-art metallization schemes. Electricalmeasurements over a wide range of temperatures down to cryogenictemperatures reveal the limited potential of cooling to reduce resistivityof conductors as lateral dimensions will be shrinked down to the sub-100nmregime. By down scaling of copper diffusion barriers in damascene trenches,barrier functionality was demonstrated after high temperature anneals andexcessive bias-temperature stress tests for films meeting or even exceedingend-of-roadmap thickness requirements. An analysis of the temperaturedependence of the leakage current measured at very high electric fieldsapplied between neighboring damascene lines suggests the conductionmechanism in the SiO2 used as intermetal dielectric to beFrenkel-Poole type rather than Schottky emission. Electromigration lifetimes of sub-100nm copper lines embedded in oxide were found to becomparable with those obtained for similar structures fabricated withtoday's feature sizes.