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Effects of Top Insulator Overlap on the Stability in Hydrogenated Amorphous Silicon Thin Film Transistors

Published online by Cambridge University Press:  16 February 2011

H.S. Choi
Affiliation:
Department of Electrical Engineering, Seoul National University, San 56–1, Shinrim-dong, Kwanak-ku, Seoul 151–742, Korea
Y.S. Kim
Affiliation:
Department of Electrical Engineering, Seoul National University, San 56–1, Shinrim-dong, Kwanak-ku, Seoul 151–742, Korea
S.K. Lee
Affiliation:
Department of Electrical Engineering, Seoul National University, San 56–1, Shinrim-dong, Kwanak-ku, Seoul 151–742, Korea
J.K. Yoon
Affiliation:
Department of Electrical Engineering, Seoul National University, San 56–1, Shinrim-dong, Kwanak-ku, Seoul 151–742, Korea
W.S. Park
Affiliation:
Department of Electrical Engineering, Seoul National University, San 56–1, Shinrim-dong, Kwanak-ku, Seoul 151–742, Korea
Andm. K. Han
Affiliation:
Department of Electrical Engineering, Seoul National University, San 56–1, Shinrim-dong, Kwanak-ku, Seoul 151–742, Korea
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Abstract

The effects of top-insulator on the instability problems of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) have been studied. In a-Si:H TFT with top-insulator (E/S type), charge trapping into the both of top-insulator and gate insulator has been shown under the bias stress.

In order to investigate the charge trapping effects of top-insulator, we proposed a new method of Measurement. By this Method, we observed that trapped charges in top-insulator increased drain currents for positive gate bias stress, and this increment of drain currents was more serious with increasing the ratio of source/drain overlap length to channel length. It has founded that the instability problems of a-Si:H TFTs was attributed to the effects of top-insulator as well as that of gate insulator.

Type
Research Article
Copyright
Copyright © Materials Research Society 1994

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References

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