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Effects of Silicon Ion Implantation upon Thin Gate Oxide Integrity

Published online by Cambridge University Press:  26 February 2011

G. -S. Lee
Affiliation:
Samsung Electronics, Quality Control 1st Section, Kyungki-do, Korea
J. -G. Park
Affiliation:
Samsung Electronics, Quality Control 1st Section, Kyungki-do, Korea
S. -P. Choi
Affiliation:
Samsung Electronics, Quality Control 1st Section, Kyungki-do, Korea
C. -H. Shin
Affiliation:
Samsung Electronics, Quality Control 1st Section, Kyungki-do, Korea
Y. -B. Sun
Affiliation:
Samsung Electronics, Quality Control 1st Section, Kyungki-do, Korea
Y. -S. Kwak
Affiliation:
Samsung Electronics, Quality Control 1st Section, Kyungki-do, Korea
C. -K. Shin
Affiliation:
Samsung Electronics, Quality Control 1st Section, Kyungki-do, Korea
W. L. Smith
Affiliation:
Therma-Wave, Inc., Mission Falls Court, Fremont, CA 94539 U.S.A.
S. Hahn
Affiliation:
Department of Materials Science and Engineering, Stanford University, Stanford, CA 94305 U.S.A.
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Abstract

In this study, using oxide breakdown voltage and time-dependent-dielectric breakdown measurements, thermal wave modulated reflectance and chemical etching/optical microscopy, we investigated effects of Si ion implantation upon formation of D-defects and thin gate oxide integrity. Our data show that addition of Si ion implantation with a dose of up to 1013 ions/cm2 improves oxide integrity if the implantation is done at a certain step just before sacrificial oxidation in the Mb DRAM process. However, no improvement in oxide integrity is observed when the same implantation is done on the virgin wafer surfaces at the start of the same Mb DRAM process. We discuss our hypothesis that the improvement in oxide integrity is due to a reduction in the D-defect density in the near-surface region of the wafer.

Type
Research Article
Copyright
Copyright © Materials Research Society 1992

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References

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