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Effect of GaAs Surface Treatments on Lanthanum Silicate High-K Dielectric Gate Stack Properties

Published online by Cambridge University Press:  01 February 2011

Daniel J Lichtenwalner
Affiliation:
[email protected], North Carolina State University, Materials Science and Engineering, 1001 Capability Drive, 214 Research Building 1, Raleigh, NC, 27695-7919, United States, 919-515-6624, 919-515-3419
Rahul Suri
Affiliation:
[email protected], North Carolina State University, Electrical and Computer Engineering, Raleigh, NC, 27695-7920, United States
Veena Misra
Affiliation:
[email protected], North Carolina State University, Electrical and Computer Engineering, Raleigh, NC, 27695-7920, United States
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Abstract

The properties of lanthanum silicate (LaSiOx) gate stacks on GaAs substrates have been examined, comparing different GaAs pretreatments; namely a) as-received, b) HCl-treated, and c) sulphur-treated. X-ray photoelectron spectroscopy of the As 3d, Ga 3d, and Ga 2p binding energy peaks were used to reveal the chemical nature of the stacks. After a 400 °C in situ anneal in 10−6 torr pO2, the LaSiOx chemically reduces the As oxides from the as-received GaAs, while Ga oxide species remain. HCl and S-treated GaAs similarly show no As oxides, and a much smaller degree of Ga oxides than the as-received case. The Ga-S bonding may be responsible for lowering the tendency towards Ga oxidation for the S-treated case. On p-type, Zn-doped GaAs, 3.0 nm lanthanum silicate films produce MOS device EOT values of 2.38 nm, 1.51 nm, and 1.37 nm, on as-received, HCl-treated, and S-treated substrates, respectively. The high EOT for the as-received GaAs corresponds to the thicker Ga oxide and elemental As at the interface. The decreases in both Ga oxide and elemental As at the interface of the S-treated stack appears to be related to it having the lowest EOT devices.

Type
Research Article
Copyright
Copyright © Materials Research Society 2008

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References

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