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Effect of Annealing on the Characteristics of Silicon Implanted Nano/trap Crystal Memories

Published online by Cambridge University Press:  15 February 2011

T.S. Kalkur ,
Nick Cramer ,
Elliott Philofsky  and
Lee Kammerdiner
T.S. Kalkur
Affiliation:
Microelectronics Research Laboratories Department of Electrical and Computer Engineering University of Colorado at Colorado Springs Colorado Springs, CO 80933-7150
Nick Cramer
Affiliation:
Applied Ceramics Research Company Colorado Springs, CO 80919
Elliott Philofsky
Affiliation:
Applied Ceramics Research Company Colorado Springs, CO 80919
Lee Kammerdiner
Affiliation:
Applied Ceramics Research Company Colorado Springs, CO 80919
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Abstract

In this paper we are presenting the results of silicon nano-trap memory fabricated by implanting high dose silicon into gate oxide of thickness 30 nm. The gate oxide was grown by dry oxidation. Capacitance versus voltage characteristics of MOS (metal oxide silicon) structures with silicon implanted samples annealed in nitrogen environment at a temperature of 950 °C show a memory window depending on the applied DC bias voltage. A memory window of 3V was obtained for an applied bias voltage of ± 10V. Annealing of the MOS structures in a furnace at a temperature of 800 °C for 30 minutes in oxygen resulted in complete loss or collapse of the memory window. Annealing the samples rapid thermally in oxygen environment at 800 oC for 30 seconds, resulted in a memory window of about 2 Volts for an applied voltage of ± 14V.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 777: Symposium A – Nanostructuring Materials with Energetic Beams , 2003 , T5.7
Copyright
Copyright © Materials Research Society 2003

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